417 lines
14 KiB
C
417 lines
14 KiB
C
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// Copyright 2012 the V8 project authors. All rights reserved.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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// * Neither the name of Google Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// This file is an internal atomic implementation, use atomicops.h instead.
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#ifndef V8_ATOMICOPS_INTERNALS_ARM_GCC_H_
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#define V8_ATOMICOPS_INTERNALS_ARM_GCC_H_
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namespace v8 {
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namespace internal {
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inline void MemoryBarrier() { /* Not used. */ }
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inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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Atomic32 prev;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"0: \n\t"
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"ldxr %w[prev], [%[ptr]] \n\t" // Load the previous value.
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"cmp %w[prev], %w[old_value] \n\t"
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"bne 1f \n\t"
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"stxr %w[temp], %w[new_value], [%[ptr]]\n\t" // Try to store the new value.
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"cbnz %w[temp], 0b \n\t" // Retry if it did not work.
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"1: \n\t"
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"clrex \n\t" // In case we didn't swap.
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: [prev]"=&r" (prev),
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[temp]"=&r" (temp)
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: [ptr]"r" (ptr),
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[old_value]"r" (old_value),
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[new_value]"r" (new_value)
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: "memory", "cc"
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); // NOLINT
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return prev;
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}
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inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
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Atomic32 new_value) {
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Atomic32 result;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"0: \n\t"
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"ldxr %w[result], [%[ptr]] \n\t" // Load the previous value.
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"stxr %w[temp], %w[new_value], [%[ptr]]\n\t" // Try to store the new value.
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"cbnz %w[temp], 0b \n\t" // Retry if it did not work.
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: [result]"=&r" (result),
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[temp]"=&r" (temp)
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: [ptr]"r" (ptr),
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[new_value]"r" (new_value)
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: "memory"
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); // NOLINT
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return result;
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}
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inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
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Atomic32 increment) {
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Atomic32 result;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"0: \n\t"
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"ldxr %w[result], [%[ptr]] \n\t" // Load the previous value.
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"add %w[result], %w[result], %w[increment]\n\t"
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"stxr %w[temp], %w[result], [%[ptr]] \n\t" // Try to store the result.
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"cbnz %w[temp], 0b \n\t" // Retry on failure.
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: [result]"=&r" (result),
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[temp]"=&r" (temp)
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: [ptr]"r" (ptr),
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[increment]"r" (increment)
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: "memory"
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); // NOLINT
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return result;
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}
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inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
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Atomic32 increment) {
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Atomic32 result;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"dmb ish \n\t" // Data memory barrier.
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"0: \n\t"
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"ldxr %w[result], [%[ptr]] \n\t" // Load the previous value.
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"add %w[result], %w[result], %w[increment]\n\t"
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"stxr %w[temp], %w[result], [%[ptr]] \n\t" // Try to store the result.
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"cbnz %w[temp], 0b \n\t" // Retry on failure.
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"dmb ish \n\t" // Data memory barrier.
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: [result]"=&r" (result),
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[temp]"=&r" (temp)
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: [ptr]"r" (ptr),
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[increment]"r" (increment)
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: "memory"
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); // NOLINT
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return result;
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}
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inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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Atomic32 prev;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"0: \n\t"
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"ldxr %w[prev], [%[ptr]] \n\t" // Load the previous value.
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"cmp %w[prev], %w[old_value] \n\t"
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"bne 1f \n\t"
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"stxr %w[temp], %w[new_value], [%[ptr]]\n\t" // Try to store the new value.
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"cbnz %w[temp], 0b \n\t" // Retry if it did not work.
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"dmb ish \n\t" // Data memory barrier.
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"1: \n\t"
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// If the compare failed the 'dmb' is unnecessary, but we still need a
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// 'clrex'.
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"clrex \n\t"
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: [prev]"=&r" (prev),
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[temp]"=&r" (temp)
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: [ptr]"r" (ptr),
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[old_value]"r" (old_value),
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[new_value]"r" (new_value)
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: "memory", "cc"
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); // NOLINT
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return prev;
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}
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inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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Atomic32 prev;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"dmb ish \n\t" // Data memory barrier.
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"0: \n\t"
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"ldxr %w[prev], [%[ptr]] \n\t" // Load the previous value.
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"cmp %w[prev], %w[old_value] \n\t"
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"bne 1f \n\t"
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"stxr %w[temp], %w[new_value], [%[ptr]]\n\t" // Try to store the new value.
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"cbnz %w[temp], 0b \n\t" // Retry if it did not work.
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"1: \n\t"
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// If the compare failed the we still need a 'clrex'.
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"clrex \n\t"
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: [prev]"=&r" (prev),
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[temp]"=&r" (temp)
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: [ptr]"r" (ptr),
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[old_value]"r" (old_value),
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[new_value]"r" (new_value)
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: "memory", "cc"
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); // NOLINT
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return prev;
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}
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inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
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*ptr = value;
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}
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inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
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*ptr = value;
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__asm__ __volatile__ ( // NOLINT
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"dmb ish \n\t" // Data memory barrier.
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::: "memory" // Prevent gcc from reordering before the store above.
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); // NOLINT
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}
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inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
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__asm__ __volatile__ ( // NOLINT
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"dmb ish \n\t" // Data memory barrier.
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::: "memory" // Prevent gcc from reordering after the store below.
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); // NOLINT
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*ptr = value;
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}
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inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) {
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return *ptr;
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}
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inline Atomic32 Acquire_Load(volatile const Atomic32* ptr) {
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Atomic32 value = *ptr;
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__asm__ __volatile__ ( // NOLINT
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"dmb ish \n\t" // Data memory barrier.
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::: "memory" // Prevent gcc from reordering before the load above.
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); // NOLINT
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return value;
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}
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inline Atomic32 Release_Load(volatile const Atomic32* ptr) {
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__asm__ __volatile__ ( // NOLINT
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"dmb ish \n\t" // Data memory barrier.
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::: "memory" // Prevent gcc from reordering after the load below.
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); // NOLINT
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return *ptr;
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}
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// 64-bit versions of the operations.
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// See the 32-bit versions for comments.
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inline Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value) {
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Atomic64 prev;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"0: \n\t"
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"ldxr %[prev], [%[ptr]] \n\t"
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"cmp %[prev], %[old_value] \n\t"
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"bne 1f \n\t"
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"stxr %w[temp], %[new_value], [%[ptr]] \n\t"
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"cbnz %w[temp], 0b \n\t"
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"1: \n\t"
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"clrex \n\t"
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: [prev]"=&r" (prev),
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[temp]"=&r" (temp)
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: [ptr]"r" (ptr),
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[old_value]"r" (old_value),
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[new_value]"r" (new_value)
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: "memory", "cc"
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); // NOLINT
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return prev;
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}
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inline Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr,
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Atomic64 new_value) {
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Atomic64 result;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"0: \n\t"
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"ldxr %[result], [%[ptr]] \n\t"
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"stxr %w[temp], %[new_value], [%[ptr]] \n\t"
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"cbnz %w[temp], 0b \n\t"
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: [result]"=&r" (result),
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[temp]"=&r" (temp)
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: [ptr]"r" (ptr),
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[new_value]"r" (new_value)
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: "memory"
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); // NOLINT
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return result;
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}
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inline Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr,
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Atomic64 increment) {
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Atomic64 result;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"0: \n\t"
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"ldxr %[result], [%[ptr]] \n\t"
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"add %[result], %[result], %[increment] \n\t"
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"stxr %w[temp], %[result], [%[ptr]] \n\t"
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"cbnz %w[temp], 0b \n\t"
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: [result]"=&r" (result),
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[temp]"=&r" (temp)
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: [ptr]"r" (ptr),
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[increment]"r" (increment)
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: "memory"
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); // NOLINT
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return result;
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}
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inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr,
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Atomic64 increment) {
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Atomic64 result;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"dmb ish \n\t"
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"0: \n\t"
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"ldxr %[result], [%[ptr]] \n\t"
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"add %[result], %[result], %[increment] \n\t"
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"stxr %w[temp], %[result], [%[ptr]] \n\t"
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"cbnz %w[temp], 0b \n\t"
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"dmb ish \n\t"
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: [result]"=&r" (result),
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[temp]"=&r" (temp)
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: [ptr]"r" (ptr),
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[increment]"r" (increment)
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: "memory"
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); // NOLINT
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return result;
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}
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inline Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value) {
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Atomic64 prev;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"0: \n\t"
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"ldxr %[prev], [%[ptr]] \n\t"
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"cmp %[prev], %[old_value] \n\t"
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"bne 1f \n\t"
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"stxr %w[temp], %[new_value], [%[ptr]] \n\t"
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"cbnz %w[temp], 0b \n\t"
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"dmb ish \n\t"
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"1: \n\t"
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"clrex \n\t"
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: [prev]"=&r" (prev),
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[temp]"=&r" (temp)
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: [ptr]"r" (ptr),
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[old_value]"r" (old_value),
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[new_value]"r" (new_value)
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: "memory", "cc"
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); // NOLINT
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return prev;
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}
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inline Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value) {
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Atomic64 prev;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"dmb ish \n\t"
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"0: \n\t"
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|
|
"ldxr %[prev], [%[ptr]] \n\t"
|
||
|
|
"cmp %[prev], %[old_value] \n\t"
|
||
|
|
"bne 1f \n\t"
|
||
|
|
"stxr %w[temp], %[new_value], [%[ptr]] \n\t"
|
||
|
|
"cbnz %w[temp], 0b \n\t"
|
||
|
|
"1: \n\t"
|
||
|
|
"clrex \n\t"
|
||
|
|
: [prev]"=&r" (prev),
|
||
|
|
[temp]"=&r" (temp)
|
||
|
|
: [ptr]"r" (ptr),
|
||
|
|
[old_value]"r" (old_value),
|
||
|
|
[new_value]"r" (new_value)
|
||
|
|
: "memory", "cc"
|
||
|
|
); // NOLINT
|
||
|
|
|
||
|
|
return prev;
|
||
|
|
}
|
||
|
|
|
||
|
|
inline void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value) {
|
||
|
|
*ptr = value;
|
||
|
|
}
|
||
|
|
|
||
|
|
inline void Acquire_Store(volatile Atomic64* ptr, Atomic64 value) {
|
||
|
|
*ptr = value;
|
||
|
|
__asm__ __volatile__ ( // NOLINT
|
||
|
|
"dmb ish \n\t"
|
||
|
|
::: "memory"
|
||
|
|
); // NOLINT
|
||
|
|
}
|
||
|
|
|
||
|
|
inline void Release_Store(volatile Atomic64* ptr, Atomic64 value) {
|
||
|
|
__asm__ __volatile__ ( // NOLINT
|
||
|
|
"dmb ish \n\t"
|
||
|
|
::: "memory"
|
||
|
|
); // NOLINT
|
||
|
|
*ptr = value;
|
||
|
|
}
|
||
|
|
|
||
|
|
inline Atomic64 NoBarrier_Load(volatile const Atomic64* ptr) {
|
||
|
|
return *ptr;
|
||
|
|
}
|
||
|
|
|
||
|
|
inline Atomic64 Acquire_Load(volatile const Atomic64* ptr) {
|
||
|
|
Atomic64 value = *ptr;
|
||
|
|
__asm__ __volatile__ ( // NOLINT
|
||
|
|
"dmb ish \n\t"
|
||
|
|
::: "memory"
|
||
|
|
); // NOLINT
|
||
|
|
return value;
|
||
|
|
}
|
||
|
|
|
||
|
|
inline Atomic64 Release_Load(volatile const Atomic64* ptr) {
|
||
|
|
__asm__ __volatile__ ( // NOLINT
|
||
|
|
"dmb ish \n\t"
|
||
|
|
::: "memory"
|
||
|
|
); // NOLINT
|
||
|
|
return *ptr;
|
||
|
|
}
|
||
|
|
|
||
|
|
} } // namespace v8::internal
|
||
|
|
|
||
|
|
#endif // V8_ATOMICOPS_INTERNALS_ARM_GCC_H_
|