2010-02-04 20:36:58 +00:00
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// Copyright (c) 1994-2006 Sun Microsystems Inc.
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// All Rights Reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// - Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// - Redistribution in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// - Neither the name of Sun Microsystems or the names of contributors may
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// be used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// The original source code covered by the above license above has been
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// modified significantly by Google Inc.
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// Copyright 2010 the V8 project authors. All rights reserved.
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#ifndef V8_MIPS_ASSEMBLER_MIPS_H_
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#define V8_MIPS_ASSEMBLER_MIPS_H_
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#include <stdio.h>
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#include "assembler.h"
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#include "constants-mips.h"
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#include "serialize.h"
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using namespace assembler::mips;
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namespace v8 {
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namespace internal {
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// CPU Registers.
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//
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// 1) We would prefer to use an enum, but enum values are assignment-
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// compatible with int, which has caused code-generation bugs.
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//
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// 2) We would prefer to use a class instead of a struct but we don't like
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// the register initialization to depend on the particular initialization
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// order (which appears to be different on OS X, Linux, and Windows for the
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// installed versions of C++ we tried). Using a struct permits C-style
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// "initialization". Also, the Register objects cannot be const as this
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// forces initialization stubs in MSVC, making us dependent on initialization
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// order.
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//
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// 3) By not using an enum, we are possibly preventing the compiler from
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// doing certain constant folds, which may significantly reduce the
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// code generated for some assembly instructions (because they boil down
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// to a few constants). If this is a problem, we could change the code
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// such that we use an enum in optimized mode, and the struct in debug
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// mode. This way we get the compile-time error checking in debug mode
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// and best performance in optimized code.
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// -----------------------------------------------------------------------------
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// Implementation of Register and FPURegister
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// Core register.
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struct Register {
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bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
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bool is(Register reg) const { return code_ == reg.code_; }
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int code() const {
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ASSERT(is_valid());
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return code_;
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}
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int bit() const {
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ASSERT(is_valid());
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return 1 << code_;
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}
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// Unfortunately we can't make this private in a struct.
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int code_;
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};
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extern const Register no_reg;
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extern const Register zero_reg;
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extern const Register at;
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extern const Register v0;
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extern const Register v1;
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extern const Register a0;
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extern const Register a1;
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extern const Register a2;
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extern const Register a3;
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extern const Register t0;
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extern const Register t1;
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extern const Register t2;
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extern const Register t3;
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extern const Register t4;
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extern const Register t5;
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extern const Register t6;
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extern const Register t7;
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extern const Register s0;
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extern const Register s1;
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extern const Register s2;
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extern const Register s3;
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extern const Register s4;
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extern const Register s5;
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extern const Register s6;
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extern const Register s7;
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extern const Register t8;
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extern const Register t9;
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extern const Register k0;
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extern const Register k1;
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extern const Register gp;
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extern const Register sp;
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extern const Register s8_fp;
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extern const Register ra;
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int ToNumber(Register reg);
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Register ToRegister(int num);
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// Coprocessor register.
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struct FPURegister {
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bool is_valid() const { return 0 <= code_ && code_ < kNumFPURegister ; }
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bool is(FPURegister creg) const { return code_ == creg.code_; }
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int code() const {
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ASSERT(is_valid());
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return code_;
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}
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int bit() const {
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ASSERT(is_valid());
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return 1 << code_;
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}
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// Unfortunately we can't make this private in a struct.
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int code_;
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};
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extern const FPURegister no_creg;
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extern const FPURegister f0;
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extern const FPURegister f1;
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extern const FPURegister f2;
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extern const FPURegister f3;
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extern const FPURegister f4;
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extern const FPURegister f5;
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extern const FPURegister f6;
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extern const FPURegister f7;
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extern const FPURegister f8;
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extern const FPURegister f9;
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extern const FPURegister f10;
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extern const FPURegister f11;
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extern const FPURegister f12; // arg
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extern const FPURegister f13;
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extern const FPURegister f14; // arg
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extern const FPURegister f15;
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extern const FPURegister f16;
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extern const FPURegister f17;
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extern const FPURegister f18;
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extern const FPURegister f19;
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extern const FPURegister f20;
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extern const FPURegister f21;
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extern const FPURegister f22;
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extern const FPURegister f23;
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extern const FPURegister f24;
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extern const FPURegister f25;
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extern const FPURegister f26;
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extern const FPURegister f27;
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extern const FPURegister f28;
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extern const FPURegister f29;
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extern const FPURegister f30;
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extern const FPURegister f31;
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// Returns the equivalent of !cc.
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// Negation of the default no_condition (-1) results in a non-default
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// no_condition value (-2). As long as tests for no_condition check
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// for condition < 0, this will work as expected.
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inline Condition NegateCondition(Condition cc);
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inline Condition ReverseCondition(Condition cc) {
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switch (cc) {
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case Uless:
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return Ugreater;
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case Ugreater:
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return Uless;
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case Ugreater_equal:
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return Uless_equal;
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case Uless_equal:
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return Ugreater_equal;
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case less:
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return greater;
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case greater:
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return less;
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case greater_equal:
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return less_equal;
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case less_equal:
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return greater_equal;
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default:
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return cc;
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};
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}
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enum Hint {
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no_hint = 0
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};
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inline Hint NegateHint(Hint hint) {
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return no_hint;
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}
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// -----------------------------------------------------------------------------
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// Machine instruction Operands.
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// Class Operand represents a shifter operand in data processing instructions.
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class Operand BASE_EMBEDDED {
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public:
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// Immediate.
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INLINE(explicit Operand(int32_t immediate,
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RelocInfo::Mode rmode = RelocInfo::NONE));
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INLINE(explicit Operand(const ExternalReference& f));
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INLINE(explicit Operand(const char* s));
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INLINE(explicit Operand(Object** opp));
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INLINE(explicit Operand(Context** cpp));
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explicit Operand(Handle<Object> handle);
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INLINE(explicit Operand(Smi* value));
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// Register.
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INLINE(explicit Operand(Register rm));
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// Return true if this is a register operand.
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INLINE(bool is_reg() const);
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Register rm() const { return rm_; }
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private:
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Register rm_;
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int32_t imm32_; // Valid if rm_ == no_reg
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RelocInfo::Mode rmode_;
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friend class Assembler;
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friend class MacroAssembler;
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};
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// On MIPS we have only one adressing mode with base_reg + offset.
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// Class MemOperand represents a memory operand in load and store instructions.
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class MemOperand : public Operand {
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public:
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explicit MemOperand(Register rn, int16_t offset = 0);
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private:
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int16_t offset_;
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friend class Assembler;
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};
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class Assembler : public Malloced {
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public:
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// Create an assembler. Instructions and relocation information are emitted
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// into a buffer, with the instructions starting from the beginning and the
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// relocation information starting from the end of the buffer. See CodeDesc
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// for a detailed comment on the layout (globals.h).
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//
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// If the provided buffer is NULL, the assembler allocates and grows its own
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// buffer, and buffer_size determines the initial buffer size. The buffer is
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// owned by the assembler and deallocated upon destruction of the assembler.
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//
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// If the provided buffer is not NULL, the assembler uses the provided buffer
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// for code generation and assumes its size to be buffer_size. If the buffer
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// is too small, a fatal error occurs. No deallocation of the buffer is done
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// upon destruction of the assembler.
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Assembler(void* buffer, int buffer_size);
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~Assembler();
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// GetCode emits any pending (non-emitted) code and fills the descriptor
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// desc. GetCode() is idempotent; it returns the same result if no other
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// Assembler functions are invoked in between GetCode() calls.
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void GetCode(CodeDesc* desc);
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// Label operations & relative jumps (PPUM Appendix D).
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//
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// Takes a branch opcode (cc) and a label (L) and generates
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// either a backward branch or a forward branch and links it
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// to the label fixup chain. Usage:
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//
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// Label L; // unbound label
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// j(cc, &L); // forward branch to unbound label
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// bind(&L); // bind label to the current pc
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// j(cc, &L); // backward branch to bound label
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// bind(&L); // illegal: a label may be bound only once
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//
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// Note: The same Label can be used for forward and backward branches
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// but it may be bound only once.
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void bind(Label* L); // binds an unbound label L to the current code position
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// Returns the branch offset to the given label from the current code position
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// Links the label to the current position if it is still unbound
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// Manages the jump elimination optimization if the second parameter is true.
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int32_t branch_offset(Label* L, bool jump_elimination_allowed);
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int32_t shifted_branch_offset(Label* L, bool jump_elimination_allowed) {
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int32_t o = branch_offset(L, jump_elimination_allowed);
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ASSERT((o & 3) == 0); // Assert the offset is aligned.
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return o >> 2;
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}
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// Puts a labels target address at the given position.
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// The high 8 bits are set to zero.
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void label_at_put(Label* L, int at_offset);
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// Size of an instruction.
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static const int kInstrSize = sizeof(Instr);
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// Difference between address of current opcode and target address offset.
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static const int kBranchPCOffset = 4;
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// Read/Modify the code target address in the branch/call instruction at pc.
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static Address target_address_at(Address pc);
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static void set_target_address_at(Address pc, Address target);
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// This sets the branch destination (which gets loaded at the call address).
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// This is for calls and branches within generated code.
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inline static void set_target_at(Address instruction_payload,
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Address target) {
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set_target_address_at(instruction_payload, target);
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}
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// This sets the branch destination.
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// This is for calls and branches to runtime code.
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inline static void set_external_target_at(Address instruction_payload,
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Address target) {
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set_target_address_at(instruction_payload, target);
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}
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static const int kCallTargetSize = 3 * kPointerSize;
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static const int kExternalTargetSize = 3 * kPointerSize;
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// Distance between the instruction referring to the address of the call
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// target and the return address.
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static const int kCallTargetAddressOffset = 4 * kInstrSize;
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// Distance between start of patched return sequence and the emitted address
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// to jump to.
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static const int kPatchReturnSequenceAddressOffset = kInstrSize;
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// ---------------------------------------------------------------------------
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// Code generation.
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void nop() { sll(zero_reg, zero_reg, 0); }
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//------- Branch and jump instructions --------
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// We don't use likely variant of instructions.
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void b(int16_t offset);
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void b(Label* L) { b(branch_offset(L, false)>>2); }
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void bal(int16_t offset);
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void bal(Label* L) { bal(branch_offset(L, false)>>2); }
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void beq(Register rs, Register rt, int16_t offset);
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void beq(Register rs, Register rt, Label* L) {
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beq(rs, rt, branch_offset(L, false) >> 2);
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}
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void bgez(Register rs, int16_t offset);
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void bgezal(Register rs, int16_t offset);
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void bgtz(Register rs, int16_t offset);
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void blez(Register rs, int16_t offset);
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void bltz(Register rs, int16_t offset);
|
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void bltzal(Register rs, int16_t offset);
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void bne(Register rs, Register rt, int16_t offset);
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void bne(Register rs, Register rt, Label* L) {
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|
bne(rs, rt, branch_offset(L, false)>>2);
|
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|
}
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// Never use the int16_t b(l)cond version with a branch offset
|
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// instead of using the Label* version. See Twiki for infos.
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// Jump targets must be in the current 256 MB-aligned region. ie 28 bits.
|
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void j(int32_t target);
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|
void jal(int32_t target);
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void jalr(Register rs, Register rd = ra);
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void jr(Register target);
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//-------Data-processing-instructions---------
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// Arithmetic.
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|
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void add(Register rd, Register rs, Register rt);
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void addu(Register rd, Register rs, Register rt);
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void sub(Register rd, Register rs, Register rt);
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void subu(Register rd, Register rs, Register rt);
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void mult(Register rs, Register rt);
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void multu(Register rs, Register rt);
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void div(Register rs, Register rt);
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void divu(Register rs, Register rt);
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void mul(Register rd, Register rs, Register rt);
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void addi(Register rd, Register rs, int32_t j);
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void addiu(Register rd, Register rs, int32_t j);
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|
// Logical.
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|
void and_(Register rd, Register rs, Register rt);
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void or_(Register rd, Register rs, Register rt);
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void xor_(Register rd, Register rs, Register rt);
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void nor(Register rd, Register rs, Register rt);
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void andi(Register rd, Register rs, int32_t j);
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|
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void ori(Register rd, Register rs, int32_t j);
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|
|
void xori(Register rd, Register rs, int32_t j);
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|
|
void lui(Register rd, int32_t j);
|
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|
|
// Shifts.
|
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|
|
void sll(Register rd, Register rt, uint16_t sa);
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|
void sllv(Register rd, Register rt, Register rs);
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|
void srl(Register rd, Register rt, uint16_t sa);
|
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|
|
void srlv(Register rd, Register rt, Register rs);
|
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|
|
void sra(Register rt, Register rd, uint16_t sa);
|
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|
|
void srav(Register rt, Register rd, Register rs);
|
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|
|
//------------Memory-instructions-------------
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|
|
void lb(Register rd, const MemOperand& rs);
|
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|
|
void lbu(Register rd, const MemOperand& rs);
|
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|
|
void lw(Register rd, const MemOperand& rs);
|
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|
|
void sb(Register rd, const MemOperand& rs);
|
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|
|
void sw(Register rd, const MemOperand& rs);
|
|
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|
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|
|
//-------------Misc-instructions--------------
|
|
|
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|
|
// Break / Trap instructions.
|
|
|
|
void break_(uint32_t code);
|
|
|
|
void tge(Register rs, Register rt, uint16_t code);
|
|
|
|
void tgeu(Register rs, Register rt, uint16_t code);
|
|
|
|
void tlt(Register rs, Register rt, uint16_t code);
|
|
|
|
void tltu(Register rs, Register rt, uint16_t code);
|
|
|
|
void teq(Register rs, Register rt, uint16_t code);
|
|
|
|
void tne(Register rs, Register rt, uint16_t code);
|
|
|
|
|
|
|
|
// Move from HI/LO register.
|
|
|
|
void mfhi(Register rd);
|
|
|
|
void mflo(Register rd);
|
|
|
|
|
|
|
|
// Set on less than.
|
|
|
|
void slt(Register rd, Register rs, Register rt);
|
|
|
|
void sltu(Register rd, Register rs, Register rt);
|
|
|
|
void slti(Register rd, Register rs, int32_t j);
|
|
|
|
void sltiu(Register rd, Register rs, int32_t j);
|
|
|
|
|
|
|
|
|
|
|
|
//--------Coprocessor-instructions----------------
|
|
|
|
|
|
|
|
// Load, store, and move.
|
|
|
|
void lwc1(FPURegister fd, const MemOperand& src);
|
|
|
|
void ldc1(FPURegister fd, const MemOperand& src);
|
|
|
|
|
|
|
|
void swc1(FPURegister fs, const MemOperand& dst);
|
|
|
|
void sdc1(FPURegister fs, const MemOperand& dst);
|
|
|
|
|
|
|
|
// When paired with MTC1 to write a value to a 64-bit FPR, the MTC1 must be
|
|
|
|
// executed first, followed by the MTHC1.
|
|
|
|
void mtc1(FPURegister fs, Register rt);
|
|
|
|
void mthc1(FPURegister fs, Register rt);
|
|
|
|
void mfc1(FPURegister fs, Register rt);
|
|
|
|
void mfhc1(FPURegister fs, Register rt);
|
|
|
|
|
|
|
|
// Conversion.
|
|
|
|
void cvt_w_s(FPURegister fd, FPURegister fs);
|
|
|
|
void cvt_w_d(FPURegister fd, FPURegister fs);
|
|
|
|
|
|
|
|
void cvt_l_s(FPURegister fd, FPURegister fs);
|
|
|
|
void cvt_l_d(FPURegister fd, FPURegister fs);
|
|
|
|
|
|
|
|
void cvt_s_w(FPURegister fd, FPURegister fs);
|
|
|
|
void cvt_s_l(FPURegister fd, FPURegister fs);
|
|
|
|
void cvt_s_d(FPURegister fd, FPURegister fs);
|
|
|
|
|
|
|
|
void cvt_d_w(FPURegister fd, FPURegister fs);
|
|
|
|
void cvt_d_l(FPURegister fd, FPURegister fs);
|
|
|
|
void cvt_d_s(FPURegister fd, FPURegister fs);
|
|
|
|
|
|
|
|
// Conditions and branches.
|
|
|
|
void c(FPUCondition cond, SecondaryField fmt,
|
|
|
|
FPURegister ft, FPURegister fs, uint16_t cc = 0);
|
|
|
|
|
|
|
|
void bc1f(int16_t offset, uint16_t cc = 0);
|
|
|
|
void bc1f(Label* L, uint16_t cc = 0) { bc1f(branch_offset(L, false)>>2, cc); }
|
|
|
|
void bc1t(int16_t offset, uint16_t cc = 0);
|
|
|
|
void bc1t(Label* L, uint16_t cc = 0) { bc1t(branch_offset(L, false)>>2, cc); }
|
|
|
|
|
|
|
|
|
|
|
|
// Check the code size generated from label to here.
|
|
|
|
int InstructionsGeneratedSince(Label* l) {
|
|
|
|
return (pc_offset() - l->pos()) / kInstrSize;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Debugging.
|
|
|
|
|
|
|
|
// Mark address of the ExitJSFrame code.
|
|
|
|
void RecordJSReturn();
|
|
|
|
|
|
|
|
// Record a comment relocation entry that can be used by a disassembler.
|
|
|
|
// Use --debug_code to enable.
|
|
|
|
void RecordComment(const char* msg);
|
|
|
|
|
|
|
|
void RecordPosition(int pos);
|
|
|
|
void RecordStatementPosition(int pos);
|
|
|
|
void WriteRecordedPositions();
|
|
|
|
|
|
|
|
int32_t pc_offset() const { return pc_ - buffer_; }
|
|
|
|
int32_t current_position() const { return current_position_; }
|
2010-04-21 07:32:04 +00:00
|
|
|
int32_t current_statement_position() const {
|
|
|
|
return current_statement_position_;
|
|
|
|
}
|
2010-02-04 20:36:58 +00:00
|
|
|
|
|
|
|
// Check if there is less than kGap bytes available in the buffer.
|
|
|
|
// If this is the case, we need to grow the buffer before emitting
|
|
|
|
// an instruction or relocation information.
|
|
|
|
inline bool overflow() const { return pc_ >= reloc_info_writer.pos() - kGap; }
|
|
|
|
|
|
|
|
// Get the number of bytes available in the buffer.
|
|
|
|
inline int available_space() const { return reloc_info_writer.pos() - pc_; }
|
|
|
|
|
|
|
|
protected:
|
|
|
|
int32_t buffer_space() const { return reloc_info_writer.pos() - pc_; }
|
|
|
|
|
|
|
|
// Read/patch instructions.
|
|
|
|
static Instr instr_at(byte* pc) { return *reinterpret_cast<Instr*>(pc); }
|
|
|
|
void instr_at_put(byte* pc, Instr instr) {
|
|
|
|
*reinterpret_cast<Instr*>(pc) = instr;
|
|
|
|
}
|
|
|
|
Instr instr_at(int pos) { return *reinterpret_cast<Instr*>(buffer_ + pos); }
|
|
|
|
void instr_at_put(int pos, Instr instr) {
|
|
|
|
*reinterpret_cast<Instr*>(buffer_ + pos) = instr;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Check if an instruction is a branch of some kind.
|
|
|
|
bool is_branch(Instr instr);
|
|
|
|
|
|
|
|
// Decode branch instruction at pos and return branch target pos.
|
|
|
|
int target_at(int32_t pos);
|
|
|
|
|
|
|
|
// Patch branch instruction at pos to branch to given branch target pos.
|
|
|
|
void target_at_put(int32_t pos, int32_t target_pos);
|
|
|
|
|
|
|
|
// Say if we need to relocate with this mode.
|
|
|
|
bool MustUseAt(RelocInfo::Mode rmode);
|
|
|
|
|
|
|
|
// Record reloc info for current pc_.
|
|
|
|
void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
|
|
|
|
|
|
|
|
private:
|
|
|
|
// Code buffer:
|
|
|
|
// The buffer into which code and relocation info are generated.
|
|
|
|
byte* buffer_;
|
|
|
|
int buffer_size_;
|
|
|
|
// True if the assembler owns the buffer, false if buffer is external.
|
|
|
|
bool own_buffer_;
|
|
|
|
|
|
|
|
// Buffer size and constant pool distance are checked together at regular
|
|
|
|
// intervals of kBufferCheckInterval emitted bytes.
|
|
|
|
static const int kBufferCheckInterval = 1*KB/2;
|
|
|
|
|
|
|
|
// Code generation.
|
|
|
|
// The relocation writer's position is at least kGap bytes below the end of
|
|
|
|
// the generated instructions. This is so that multi-instruction sequences do
|
|
|
|
// not have to check for overflow. The same is true for writes of large
|
|
|
|
// relocation info entries.
|
|
|
|
static const int kGap = 32;
|
|
|
|
byte* pc_; // The program counter - moves forward.
|
|
|
|
|
|
|
|
// Relocation information generation.
|
|
|
|
// Each relocation is encoded as a variable size value.
|
|
|
|
static const int kMaxRelocSize = RelocInfoWriter::kMaxSize;
|
|
|
|
RelocInfoWriter reloc_info_writer;
|
|
|
|
|
|
|
|
// The bound position, before this we cannot do instruction elimination.
|
|
|
|
int last_bound_pos_;
|
|
|
|
|
|
|
|
// Source position information.
|
|
|
|
int current_position_;
|
|
|
|
int current_statement_position_;
|
|
|
|
int written_position_;
|
|
|
|
int written_statement_position_;
|
|
|
|
|
|
|
|
// Code emission.
|
|
|
|
inline void CheckBuffer();
|
|
|
|
void GrowBuffer();
|
|
|
|
inline void emit(Instr x);
|
|
|
|
|
|
|
|
// Instruction generation.
|
|
|
|
// We have 3 different kind of encoding layout on MIPS.
|
|
|
|
// However due to many different types of objects encoded in the same fields
|
|
|
|
// we have quite a few aliases for each mode.
|
|
|
|
// Using the same structure to refer to Register and FPURegister would spare a
|
|
|
|
// few aliases, but mixing both does not look clean to me.
|
|
|
|
// Anyway we could surely implement this differently.
|
|
|
|
|
|
|
|
void GenInstrRegister(Opcode opcode,
|
|
|
|
Register rs,
|
|
|
|
Register rt,
|
|
|
|
Register rd,
|
|
|
|
uint16_t sa = 0,
|
|
|
|
SecondaryField func = NULLSF);
|
|
|
|
|
|
|
|
void GenInstrRegister(Opcode opcode,
|
|
|
|
SecondaryField fmt,
|
|
|
|
FPURegister ft,
|
|
|
|
FPURegister fs,
|
|
|
|
FPURegister fd,
|
|
|
|
SecondaryField func = NULLSF);
|
|
|
|
|
|
|
|
void GenInstrRegister(Opcode opcode,
|
|
|
|
SecondaryField fmt,
|
|
|
|
Register rt,
|
|
|
|
FPURegister fs,
|
|
|
|
FPURegister fd,
|
|
|
|
SecondaryField func = NULLSF);
|
|
|
|
|
|
|
|
|
|
|
|
void GenInstrImmediate(Opcode opcode,
|
|
|
|
Register rs,
|
|
|
|
Register rt,
|
|
|
|
int32_t j);
|
|
|
|
void GenInstrImmediate(Opcode opcode,
|
|
|
|
Register rs,
|
|
|
|
SecondaryField SF,
|
|
|
|
int32_t j);
|
|
|
|
void GenInstrImmediate(Opcode opcode,
|
|
|
|
Register r1,
|
|
|
|
FPURegister r2,
|
|
|
|
int32_t j);
|
|
|
|
|
|
|
|
|
|
|
|
void GenInstrJump(Opcode opcode,
|
|
|
|
uint32_t address);
|
|
|
|
|
|
|
|
|
|
|
|
// Labels.
|
|
|
|
void print(Label* L);
|
|
|
|
void bind_to(Label* L, int pos);
|
|
|
|
void link_to(Label* L, Label* appendix);
|
|
|
|
void next(Label* L);
|
|
|
|
|
|
|
|
friend class RegExpMacroAssemblerMIPS;
|
|
|
|
friend class RelocInfo;
|
|
|
|
};
|
|
|
|
|
|
|
|
} } // namespace v8::internal
|
|
|
|
|
|
|
|
#endif // V8_ARM_ASSEMBLER_MIPS_H_
|
|
|
|
|