2012-03-13 16:18:30 +00:00
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// Copyright 2012 the V8 project authors. All rights reserved.
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2010-02-04 20:36:58 +00:00
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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// * Neither the name of Google Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#ifndef V8_MIPS_CONSTANTS_H_
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#define V8_MIPS_CONSTANTS_H_
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// UNIMPLEMENTED_ macro for MIPS.
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2011-03-28 13:05:36 +00:00
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#ifdef DEBUG
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2010-02-04 20:36:58 +00:00
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#define UNIMPLEMENTED_MIPS() \
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v8::internal::PrintF("%s, \tline %d: \tfunction %s not implemented. \n", \
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__FILE__, __LINE__, __func__)
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2011-03-28 13:05:36 +00:00
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#else
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#define UNIMPLEMENTED_MIPS()
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#endif
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2010-02-04 20:36:58 +00:00
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#define UNSUPPORTED_MIPS() v8::internal::PrintF("Unsupported instruction.\n")
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2012-03-13 16:18:30 +00:00
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enum ArchVariants {
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kMips32r2,
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kMips32r1,
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kLoongson
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};
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2010-02-04 20:36:58 +00:00
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2011-03-28 13:05:36 +00:00
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#ifdef _MIPS_ARCH_MIPS32R2
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static const ArchVariants kArchVariant = kMips32r2;
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#elif _MIPS_ARCH_LOONGSON
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// The loongson flag refers to the LOONGSON architectures based on MIPS-III,
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// which predates (and is a subset of) the mips32r2 and r1 architectures.
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static const ArchVariants kArchVariant = kLoongson;
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#else
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static const ArchVariants kArchVariant = kMips32r1;
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#endif
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2011-05-24 07:23:32 +00:00
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#if(defined(__mips_hard_float) && __mips_hard_float != 0)
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// Use floating-point coprocessor instructions. This flag is raised when
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// -mhard-float is passed to the compiler.
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const bool IsMipsSoftFloatABI = false;
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2011-05-24 07:23:32 +00:00
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#elif(defined(__mips_soft_float) && __mips_soft_float != 0)
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// Not using floating-point coprocessor instructions. This flag is raised when
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// -msoft-float is passed to the compiler.
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const bool IsMipsSoftFloatABI = true;
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2011-05-24 07:23:32 +00:00
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#else
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const bool IsMipsSoftFloatABI = true;
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2011-05-24 07:23:32 +00:00
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#endif
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2010-02-04 20:36:58 +00:00
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// Defines constants and accessor classes to assemble, disassemble and
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// simulate MIPS32 instructions.
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//
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// See: MIPS32 Architecture For Programmers
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// Volume II: The MIPS32 Instruction Set
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// Try www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf.
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2011-03-28 13:05:36 +00:00
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namespace v8 {
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namespace internal {
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// -----------------------------------------------------------------------------
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// Registers and FPURegisters.
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// Number of general purpose registers.
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const int kNumRegisters = 32;
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const int kInvalidRegister = -1;
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// Number of registers with HI, LO, and pc.
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const int kNumSimuRegisters = 35;
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// In the simulator, the PC register is simulated as the 34th register.
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const int kPCRegister = 34;
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// Number coprocessor registers.
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const int kNumFPURegisters = 32;
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const int kInvalidFPURegister = -1;
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// FPU (coprocessor 1) control registers. Currently only FCSR is implemented.
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const int kFCSRRegister = 31;
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const int kInvalidFPUControlRegister = -1;
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2013-01-09 09:40:00 +00:00
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const uint32_t kFPUInvalidResult = static_cast<uint32_t>(1 << 31) - 1;
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// FCSR constants.
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const uint32_t kFCSRInexactFlagBit = 2;
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const uint32_t kFCSRUnderflowFlagBit = 3;
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const uint32_t kFCSROverflowFlagBit = 4;
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const uint32_t kFCSRDivideByZeroFlagBit = 5;
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const uint32_t kFCSRInvalidOpFlagBit = 6;
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const uint32_t kFCSRInexactFlagMask = 1 << kFCSRInexactFlagBit;
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const uint32_t kFCSRUnderflowFlagMask = 1 << kFCSRUnderflowFlagBit;
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const uint32_t kFCSROverflowFlagMask = 1 << kFCSROverflowFlagBit;
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const uint32_t kFCSRDivideByZeroFlagMask = 1 << kFCSRDivideByZeroFlagBit;
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const uint32_t kFCSRInvalidOpFlagMask = 1 << kFCSRInvalidOpFlagBit;
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const uint32_t kFCSRFlagMask =
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kFCSRInexactFlagMask |
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kFCSRUnderflowFlagMask |
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kFCSROverflowFlagMask |
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kFCSRDivideByZeroFlagMask |
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kFCSRInvalidOpFlagMask;
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const uint32_t kFCSRExceptionFlagMask = kFCSRFlagMask ^ kFCSRInexactFlagMask;
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// Helper functions for converting between register numbers and names.
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class Registers {
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public:
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// Return the name of the register.
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static const char* Name(int reg);
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// Lookup the register number for the name provided.
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static int Number(const char* name);
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struct RegisterAlias {
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int reg;
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const char* name;
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};
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static const int32_t kMaxValue = 0x7fffffff;
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static const int32_t kMinValue = 0x80000000;
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private:
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static const char* names_[kNumSimuRegisters];
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static const RegisterAlias aliases_[];
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};
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// Helper functions for converting between register numbers and names.
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class FPURegisters {
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public:
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// Return the name of the register.
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static const char* Name(int reg);
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// Lookup the register number for the name provided.
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static int Number(const char* name);
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struct RegisterAlias {
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int creg;
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const char* name;
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};
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private:
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static const char* names_[kNumFPURegisters];
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static const RegisterAlias aliases_[];
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};
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// -----------------------------------------------------------------------------
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// Instructions encoding constants.
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// On MIPS all instructions are 32 bits.
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typedef int32_t Instr;
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// Special Software Interrupt codes when used in the presence of the MIPS
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// simulator.
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enum SoftwareInterruptCodes {
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// Transition to C code.
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call_rt_redirected = 0xfffff
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};
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2011-05-26 07:46:18 +00:00
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// On MIPS Simulator breakpoints can have different codes:
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// - Breaks between 0 and kMaxWatchpointCode are treated as simple watchpoints,
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// the simulator will run through them and print the registers.
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// - Breaks between kMaxWatchpointCode and kMaxStopCode are treated as stop()
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// instructions (see Assembler::stop()).
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// - Breaks larger than kMaxStopCode are simple breaks, dropping you into the
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// debugger.
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2011-11-29 10:56:11 +00:00
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const uint32_t kMaxWatchpointCode = 31;
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const uint32_t kMaxStopCode = 127;
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2011-05-26 07:46:18 +00:00
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STATIC_ASSERT(kMaxWatchpointCode < kMaxStopCode);
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2010-02-04 20:36:58 +00:00
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// ----- Fields offset and length.
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const int kOpcodeShift = 26;
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const int kOpcodeBits = 6;
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const int kRsShift = 21;
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const int kRsBits = 5;
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const int kRtShift = 16;
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const int kRtBits = 5;
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const int kRdShift = 11;
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const int kRdBits = 5;
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const int kSaShift = 6;
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const int kSaBits = 5;
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const int kFunctionShift = 0;
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const int kFunctionBits = 6;
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const int kLuiShift = 16;
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const int kImm16Shift = 0;
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const int kImm16Bits = 16;
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const int kImm26Shift = 0;
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const int kImm26Bits = 26;
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const int kImm28Shift = 0;
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const int kImm28Bits = 28;
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2011-09-13 12:12:25 +00:00
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// In branches and jumps immediate fields point to words, not bytes,
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// and are therefore shifted by 2.
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const int kImmFieldShift = 2;
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const int kFsShift = 11;
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const int kFsBits = 5;
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const int kFtShift = 16;
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const int kFtBits = 5;
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const int kFdShift = 6;
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const int kFdBits = 5;
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const int kFCccShift = 8;
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const int kFCccBits = 3;
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const int kFBccShift = 18;
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const int kFBccBits = 3;
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const int kFBtrueShift = 16;
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const int kFBtrueBits = 1;
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2011-05-09 14:28:09 +00:00
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// ----- Miscellaneous useful masks.
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// Instruction bit masks.
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const int kOpcodeMask = ((1 << kOpcodeBits) - 1) << kOpcodeShift;
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const int kImm16Mask = ((1 << kImm16Bits) - 1) << kImm16Shift;
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const int kImm26Mask = ((1 << kImm26Bits) - 1) << kImm26Shift;
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const int kImm28Mask = ((1 << kImm28Bits) - 1) << kImm28Shift;
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const int kRsFieldMask = ((1 << kRsBits) - 1) << kRsShift;
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const int kRtFieldMask = ((1 << kRtBits) - 1) << kRtShift;
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const int kRdFieldMask = ((1 << kRdBits) - 1) << kRdShift;
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const int kSaFieldMask = ((1 << kSaBits) - 1) << kSaShift;
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const int kFunctionFieldMask = ((1 << kFunctionBits) - 1) << kFunctionShift;
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// Misc masks.
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const int kHiMask = 0xffff << 16;
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const int kLoMask = 0xffff;
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const int kSignMask = 0x80000000;
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const int kJumpAddrMask = (1 << (kImm26Bits + kImmFieldShift)) - 1;
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// ----- MIPS Opcodes and Function Fields.
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// We use this presentation to stay close to the table representation in
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// MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set.
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enum Opcode {
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SPECIAL = 0 << kOpcodeShift,
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REGIMM = 1 << kOpcodeShift,
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J = ((0 << 3) + 2) << kOpcodeShift,
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JAL = ((0 << 3) + 3) << kOpcodeShift,
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BEQ = ((0 << 3) + 4) << kOpcodeShift,
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BNE = ((0 << 3) + 5) << kOpcodeShift,
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BLEZ = ((0 << 3) + 6) << kOpcodeShift,
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BGTZ = ((0 << 3) + 7) << kOpcodeShift,
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ADDI = ((1 << 3) + 0) << kOpcodeShift,
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ADDIU = ((1 << 3) + 1) << kOpcodeShift,
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SLTI = ((1 << 3) + 2) << kOpcodeShift,
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SLTIU = ((1 << 3) + 3) << kOpcodeShift,
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ANDI = ((1 << 3) + 4) << kOpcodeShift,
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ORI = ((1 << 3) + 5) << kOpcodeShift,
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XORI = ((1 << 3) + 6) << kOpcodeShift,
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LUI = ((1 << 3) + 7) << kOpcodeShift,
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2011-05-09 14:28:09 +00:00
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COP1 = ((2 << 3) + 1) << kOpcodeShift, // Coprocessor 1 class.
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BEQL = ((2 << 3) + 4) << kOpcodeShift,
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BNEL = ((2 << 3) + 5) << kOpcodeShift,
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BLEZL = ((2 << 3) + 6) << kOpcodeShift,
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BGTZL = ((2 << 3) + 7) << kOpcodeShift,
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SPECIAL2 = ((3 << 3) + 4) << kOpcodeShift,
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SPECIAL3 = ((3 << 3) + 7) << kOpcodeShift,
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LB = ((4 << 3) + 0) << kOpcodeShift,
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LH = ((4 << 3) + 1) << kOpcodeShift,
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LWL = ((4 << 3) + 2) << kOpcodeShift,
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LW = ((4 << 3) + 3) << kOpcodeShift,
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LBU = ((4 << 3) + 4) << kOpcodeShift,
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2011-03-28 13:05:36 +00:00
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LHU = ((4 << 3) + 5) << kOpcodeShift,
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LWR = ((4 << 3) + 6) << kOpcodeShift,
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2010-02-04 20:36:58 +00:00
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SB = ((5 << 3) + 0) << kOpcodeShift,
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SH = ((5 << 3) + 1) << kOpcodeShift,
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SWL = ((5 << 3) + 2) << kOpcodeShift,
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2010-02-04 20:36:58 +00:00
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SW = ((5 << 3) + 3) << kOpcodeShift,
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SWR = ((5 << 3) + 6) << kOpcodeShift,
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2010-02-04 20:36:58 +00:00
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LWC1 = ((6 << 3) + 1) << kOpcodeShift,
|
|
|
|
LDC1 = ((6 << 3) + 5) << kOpcodeShift,
|
|
|
|
|
|
|
|
SWC1 = ((7 << 3) + 1) << kOpcodeShift,
|
|
|
|
SDC1 = ((7 << 3) + 5) << kOpcodeShift
|
|
|
|
};
|
|
|
|
|
|
|
|
enum SecondaryField {
|
|
|
|
// SPECIAL Encoding of Function Field.
|
|
|
|
SLL = ((0 << 3) + 0),
|
2011-09-13 12:12:25 +00:00
|
|
|
MOVCI = ((0 << 3) + 1),
|
2010-02-04 20:36:58 +00:00
|
|
|
SRL = ((0 << 3) + 2),
|
|
|
|
SRA = ((0 << 3) + 3),
|
|
|
|
SLLV = ((0 << 3) + 4),
|
|
|
|
SRLV = ((0 << 3) + 6),
|
|
|
|
SRAV = ((0 << 3) + 7),
|
|
|
|
|
|
|
|
JR = ((1 << 3) + 0),
|
|
|
|
JALR = ((1 << 3) + 1),
|
2011-03-28 13:05:36 +00:00
|
|
|
MOVZ = ((1 << 3) + 2),
|
|
|
|
MOVN = ((1 << 3) + 3),
|
2010-02-04 20:36:58 +00:00
|
|
|
BREAK = ((1 << 3) + 5),
|
|
|
|
|
|
|
|
MFHI = ((2 << 3) + 0),
|
|
|
|
MFLO = ((2 << 3) + 2),
|
|
|
|
|
|
|
|
MULT = ((3 << 3) + 0),
|
|
|
|
MULTU = ((3 << 3) + 1),
|
|
|
|
DIV = ((3 << 3) + 2),
|
|
|
|
DIVU = ((3 << 3) + 3),
|
|
|
|
|
|
|
|
ADD = ((4 << 3) + 0),
|
|
|
|
ADDU = ((4 << 3) + 1),
|
|
|
|
SUB = ((4 << 3) + 2),
|
|
|
|
SUBU = ((4 << 3) + 3),
|
|
|
|
AND = ((4 << 3) + 4),
|
|
|
|
OR = ((4 << 3) + 5),
|
|
|
|
XOR = ((4 << 3) + 6),
|
|
|
|
NOR = ((4 << 3) + 7),
|
|
|
|
|
|
|
|
SLT = ((5 << 3) + 2),
|
|
|
|
SLTU = ((5 << 3) + 3),
|
|
|
|
|
|
|
|
TGE = ((6 << 3) + 0),
|
|
|
|
TGEU = ((6 << 3) + 1),
|
|
|
|
TLT = ((6 << 3) + 2),
|
|
|
|
TLTU = ((6 << 3) + 3),
|
|
|
|
TEQ = ((6 << 3) + 4),
|
|
|
|
TNE = ((6 << 3) + 6),
|
|
|
|
|
|
|
|
// SPECIAL2 Encoding of Function Field.
|
|
|
|
MUL = ((0 << 3) + 2),
|
2011-03-28 13:05:36 +00:00
|
|
|
CLZ = ((4 << 3) + 0),
|
|
|
|
CLO = ((4 << 3) + 1),
|
|
|
|
|
|
|
|
// SPECIAL3 Encoding of Function Field.
|
|
|
|
EXT = ((0 << 3) + 0),
|
|
|
|
INS = ((0 << 3) + 4),
|
2010-02-04 20:36:58 +00:00
|
|
|
|
|
|
|
// REGIMM encoding of rt Field.
|
|
|
|
BLTZ = ((0 << 3) + 0) << 16,
|
|
|
|
BGEZ = ((0 << 3) + 1) << 16,
|
|
|
|
BLTZAL = ((2 << 3) + 0) << 16,
|
|
|
|
BGEZAL = ((2 << 3) + 1) << 16,
|
|
|
|
|
|
|
|
// COP1 Encoding of rs Field.
|
|
|
|
MFC1 = ((0 << 3) + 0) << 21,
|
2011-03-28 13:05:36 +00:00
|
|
|
CFC1 = ((0 << 3) + 2) << 21,
|
2010-02-04 20:36:58 +00:00
|
|
|
MFHC1 = ((0 << 3) + 3) << 21,
|
|
|
|
MTC1 = ((0 << 3) + 4) << 21,
|
2011-03-28 13:05:36 +00:00
|
|
|
CTC1 = ((0 << 3) + 6) << 21,
|
2010-02-04 20:36:58 +00:00
|
|
|
MTHC1 = ((0 << 3) + 7) << 21,
|
|
|
|
BC1 = ((1 << 3) + 0) << 21,
|
|
|
|
S = ((2 << 3) + 0) << 21,
|
|
|
|
D = ((2 << 3) + 1) << 21,
|
|
|
|
W = ((2 << 3) + 4) << 21,
|
|
|
|
L = ((2 << 3) + 5) << 21,
|
|
|
|
PS = ((2 << 3) + 6) << 21,
|
|
|
|
// COP1 Encoding of Function Field When rs=S.
|
2011-03-28 13:05:36 +00:00
|
|
|
ROUND_L_S = ((1 << 3) + 0),
|
|
|
|
TRUNC_L_S = ((1 << 3) + 1),
|
|
|
|
CEIL_L_S = ((1 << 3) + 2),
|
|
|
|
FLOOR_L_S = ((1 << 3) + 3),
|
|
|
|
ROUND_W_S = ((1 << 3) + 4),
|
|
|
|
TRUNC_W_S = ((1 << 3) + 5),
|
|
|
|
CEIL_W_S = ((1 << 3) + 6),
|
|
|
|
FLOOR_W_S = ((1 << 3) + 7),
|
2010-02-04 20:36:58 +00:00
|
|
|
CVT_D_S = ((4 << 3) + 1),
|
|
|
|
CVT_W_S = ((4 << 3) + 4),
|
|
|
|
CVT_L_S = ((4 << 3) + 5),
|
|
|
|
CVT_PS_S = ((4 << 3) + 6),
|
|
|
|
// COP1 Encoding of Function Field When rs=D.
|
2011-03-28 13:05:36 +00:00
|
|
|
ADD_D = ((0 << 3) + 0),
|
|
|
|
SUB_D = ((0 << 3) + 1),
|
|
|
|
MUL_D = ((0 << 3) + 2),
|
|
|
|
DIV_D = ((0 << 3) + 3),
|
|
|
|
SQRT_D = ((0 << 3) + 4),
|
|
|
|
ABS_D = ((0 << 3) + 5),
|
|
|
|
MOV_D = ((0 << 3) + 6),
|
|
|
|
NEG_D = ((0 << 3) + 7),
|
|
|
|
ROUND_L_D = ((1 << 3) + 0),
|
|
|
|
TRUNC_L_D = ((1 << 3) + 1),
|
|
|
|
CEIL_L_D = ((1 << 3) + 2),
|
|
|
|
FLOOR_L_D = ((1 << 3) + 3),
|
|
|
|
ROUND_W_D = ((1 << 3) + 4),
|
|
|
|
TRUNC_W_D = ((1 << 3) + 5),
|
|
|
|
CEIL_W_D = ((1 << 3) + 6),
|
|
|
|
FLOOR_W_D = ((1 << 3) + 7),
|
2010-02-04 20:36:58 +00:00
|
|
|
CVT_S_D = ((4 << 3) + 0),
|
|
|
|
CVT_W_D = ((4 << 3) + 4),
|
|
|
|
CVT_L_D = ((4 << 3) + 5),
|
2011-03-28 13:05:36 +00:00
|
|
|
C_F_D = ((6 << 3) + 0),
|
|
|
|
C_UN_D = ((6 << 3) + 1),
|
|
|
|
C_EQ_D = ((6 << 3) + 2),
|
|
|
|
C_UEQ_D = ((6 << 3) + 3),
|
|
|
|
C_OLT_D = ((6 << 3) + 4),
|
|
|
|
C_ULT_D = ((6 << 3) + 5),
|
|
|
|
C_OLE_D = ((6 << 3) + 6),
|
|
|
|
C_ULE_D = ((6 << 3) + 7),
|
2010-02-04 20:36:58 +00:00
|
|
|
// COP1 Encoding of Function Field When rs=W or L.
|
|
|
|
CVT_S_W = ((4 << 3) + 0),
|
|
|
|
CVT_D_W = ((4 << 3) + 1),
|
|
|
|
CVT_S_L = ((4 << 3) + 0),
|
|
|
|
CVT_D_L = ((4 << 3) + 1),
|
|
|
|
// COP1 Encoding of Function Field When rs=PS.
|
|
|
|
|
|
|
|
NULLSF = 0
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
// ----- Emulated conditions.
|
|
|
|
// On MIPS we use this enum to abstract from conditionnal branch instructions.
|
|
|
|
// the 'U' prefix is used to specify unsigned comparisons.
|
|
|
|
enum Condition {
|
|
|
|
// Any value < 0 is considered no_condition.
|
2011-03-28 13:05:36 +00:00
|
|
|
kNoCondition = -1,
|
2010-02-04 20:36:58 +00:00
|
|
|
|
|
|
|
overflow = 0,
|
|
|
|
no_overflow = 1,
|
|
|
|
Uless = 2,
|
|
|
|
Ugreater_equal= 3,
|
|
|
|
equal = 4,
|
|
|
|
not_equal = 5,
|
|
|
|
Uless_equal = 6,
|
|
|
|
Ugreater = 7,
|
|
|
|
negative = 8,
|
|
|
|
positive = 9,
|
|
|
|
parity_even = 10,
|
|
|
|
parity_odd = 11,
|
|
|
|
less = 12,
|
|
|
|
greater_equal = 13,
|
|
|
|
less_equal = 14,
|
|
|
|
greater = 15,
|
|
|
|
|
|
|
|
cc_always = 16,
|
|
|
|
|
2011-05-09 14:28:09 +00:00
|
|
|
// Aliases.
|
2010-02-04 20:36:58 +00:00
|
|
|
carry = Uless,
|
|
|
|
not_carry = Ugreater_equal,
|
|
|
|
zero = equal,
|
|
|
|
eq = equal,
|
|
|
|
not_zero = not_equal,
|
|
|
|
ne = not_equal,
|
2011-03-28 13:05:36 +00:00
|
|
|
nz = not_equal,
|
2010-02-04 20:36:58 +00:00
|
|
|
sign = negative,
|
|
|
|
not_sign = positive,
|
2011-03-28 13:05:36 +00:00
|
|
|
mi = negative,
|
|
|
|
pl = positive,
|
|
|
|
hi = Ugreater,
|
|
|
|
ls = Uless_equal,
|
|
|
|
ge = greater_equal,
|
|
|
|
lt = less,
|
|
|
|
gt = greater,
|
|
|
|
le = less_equal,
|
|
|
|
hs = Ugreater_equal,
|
|
|
|
lo = Uless,
|
|
|
|
al = cc_always,
|
|
|
|
|
|
|
|
cc_default = kNoCondition
|
2010-02-04 20:36:58 +00:00
|
|
|
};
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
|
|
|
|
// Returns the equivalent of !cc.
|
|
|
|
// Negation of the default kNoCondition (-1) results in a non-default
|
|
|
|
// no_condition value (-2). As long as tests for no_condition check
|
|
|
|
// for condition < 0, this will work as expected.
|
|
|
|
inline Condition NegateCondition(Condition cc) {
|
|
|
|
ASSERT(cc != cc_always);
|
|
|
|
return static_cast<Condition>(cc ^ 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
inline Condition ReverseCondition(Condition cc) {
|
|
|
|
switch (cc) {
|
|
|
|
case Uless:
|
|
|
|
return Ugreater;
|
|
|
|
case Ugreater:
|
|
|
|
return Uless;
|
|
|
|
case Ugreater_equal:
|
|
|
|
return Uless_equal;
|
|
|
|
case Uless_equal:
|
|
|
|
return Ugreater_equal;
|
|
|
|
case less:
|
|
|
|
return greater;
|
|
|
|
case greater:
|
|
|
|
return less;
|
|
|
|
case greater_equal:
|
|
|
|
return less_equal;
|
|
|
|
case less_equal:
|
|
|
|
return greater_equal;
|
|
|
|
default:
|
|
|
|
return cc;
|
|
|
|
};
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2010-02-04 20:36:58 +00:00
|
|
|
// ----- Coprocessor conditions.
|
|
|
|
enum FPUCondition {
|
2011-09-13 12:12:25 +00:00
|
|
|
kNoFPUCondition = -1,
|
|
|
|
|
|
|
|
F = 0, // False.
|
|
|
|
UN = 1, // Unordered.
|
|
|
|
EQ = 2, // Equal.
|
|
|
|
UEQ = 3, // Unordered or Equal.
|
|
|
|
OLT = 4, // Ordered or Less Than.
|
|
|
|
ULT = 5, // Unordered or Less Than.
|
|
|
|
OLE = 6, // Ordered or Less Than or Equal.
|
|
|
|
ULE = 7 // Unordered or Less Than or Equal.
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
// FPU rounding modes.
|
|
|
|
enum FPURoundingMode {
|
|
|
|
RN = 0 << 0, // Round to Nearest.
|
|
|
|
RZ = 1 << 0, // Round towards zero.
|
|
|
|
RP = 2 << 0, // Round towards Plus Infinity.
|
|
|
|
RM = 3 << 0, // Round towards Minus Infinity.
|
|
|
|
|
|
|
|
// Aliases.
|
|
|
|
kRoundToNearest = RN,
|
|
|
|
kRoundToZero = RZ,
|
|
|
|
kRoundToPlusInf = RP,
|
|
|
|
kRoundToMinusInf = RM
|
|
|
|
};
|
|
|
|
|
2011-11-29 10:56:11 +00:00
|
|
|
const uint32_t kFPURoundingModeMask = 3 << 0;
|
2011-09-13 12:12:25 +00:00
|
|
|
|
|
|
|
enum CheckForInexactConversion {
|
|
|
|
kCheckForInexactConversion,
|
|
|
|
kDontCheckForInexactConversion
|
2010-02-04 20:36:58 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
// -----------------------------------------------------------------------------
|
|
|
|
// Hints.
|
|
|
|
|
|
|
|
// Branch hints are not used on the MIPS. They are defined so that they can
|
|
|
|
// appear in shared function signatures, but will be ignored in MIPS
|
|
|
|
// implementations.
|
|
|
|
enum Hint {
|
|
|
|
no_hint = 0
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
inline Hint NegateHint(Hint hint) {
|
|
|
|
return no_hint;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// -----------------------------------------------------------------------------
|
|
|
|
// Specific instructions, constants, and masks.
|
|
|
|
// These constants are declared in assembler-mips.cc, as they use named
|
|
|
|
// registers and other constants.
|
|
|
|
|
|
|
|
// addiu(sp, sp, 4) aka Pop() operation or part of Pop(r)
|
|
|
|
// operations as post-increment of sp.
|
|
|
|
extern const Instr kPopInstruction;
|
|
|
|
// addiu(sp, sp, -4) part of Push(r) operation as pre-decrement of sp.
|
|
|
|
extern const Instr kPushInstruction;
|
|
|
|
// sw(r, MemOperand(sp, 0))
|
|
|
|
extern const Instr kPushRegPattern;
|
2011-05-09 14:28:09 +00:00
|
|
|
// lw(r, MemOperand(sp, 0))
|
2011-03-28 13:05:36 +00:00
|
|
|
extern const Instr kPopRegPattern;
|
|
|
|
extern const Instr kLwRegFpOffsetPattern;
|
|
|
|
extern const Instr kSwRegFpOffsetPattern;
|
|
|
|
extern const Instr kLwRegFpNegOffsetPattern;
|
|
|
|
extern const Instr kSwRegFpNegOffsetPattern;
|
|
|
|
// A mask for the Rt register for push, pop, lw, sw instructions.
|
|
|
|
extern const Instr kRtMask;
|
|
|
|
extern const Instr kLwSwInstrTypeMask;
|
|
|
|
extern const Instr kLwSwInstrArgumentMask;
|
|
|
|
extern const Instr kLwSwOffsetMask;
|
|
|
|
|
2010-02-04 20:36:58 +00:00
|
|
|
// Break 0xfffff, reserved for redirected real time call.
|
|
|
|
const Instr rtCallRedirInstr = SPECIAL | BREAK | call_rt_redirected << 6;
|
|
|
|
// A nop instruction. (Encoding of sll 0 0 0).
|
|
|
|
const Instr nopInstr = 0;
|
|
|
|
|
|
|
|
class Instruction {
|
|
|
|
public:
|
|
|
|
enum {
|
2011-03-28 13:05:36 +00:00
|
|
|
kInstrSize = 4,
|
|
|
|
kInstrSizeLog2 = 2,
|
2010-02-04 20:36:58 +00:00
|
|
|
// On MIPS PC cannot actually be directly accessed. We behave as if PC was
|
2011-03-28 13:05:36 +00:00
|
|
|
// always the value of the current instruction being executed.
|
2010-02-04 20:36:58 +00:00
|
|
|
kPCReadOffset = 0
|
|
|
|
};
|
|
|
|
|
|
|
|
// Get the raw instruction bits.
|
|
|
|
inline Instr InstructionBits() const {
|
|
|
|
return *reinterpret_cast<const Instr*>(this);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Set the raw instruction bits to value.
|
|
|
|
inline void SetInstructionBits(Instr value) {
|
|
|
|
*reinterpret_cast<Instr*>(this) = value;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Read one particular bit out of the instruction bits.
|
|
|
|
inline int Bit(int nr) const {
|
|
|
|
return (InstructionBits() >> nr) & 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Read a bit field out of the instruction bits.
|
|
|
|
inline int Bits(int hi, int lo) const {
|
|
|
|
return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Instruction type.
|
|
|
|
enum Type {
|
|
|
|
kRegisterType,
|
|
|
|
kImmediateType,
|
|
|
|
kJumpType,
|
|
|
|
kUnsupported = -1
|
|
|
|
};
|
|
|
|
|
|
|
|
// Get the encoding type of the instruction.
|
|
|
|
Type InstructionType() const;
|
|
|
|
|
|
|
|
|
|
|
|
// Accessors for the different named fields used in the MIPS encoding.
|
2011-03-28 13:05:36 +00:00
|
|
|
inline Opcode OpcodeValue() const {
|
2010-02-04 20:36:58 +00:00
|
|
|
return static_cast<Opcode>(
|
|
|
|
Bits(kOpcodeShift + kOpcodeBits - 1, kOpcodeShift));
|
|
|
|
}
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
inline int RsValue() const {
|
2010-02-04 20:36:58 +00:00
|
|
|
ASSERT(InstructionType() == kRegisterType ||
|
|
|
|
InstructionType() == kImmediateType);
|
|
|
|
return Bits(kRsShift + kRsBits - 1, kRsShift);
|
|
|
|
}
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
inline int RtValue() const {
|
2010-02-04 20:36:58 +00:00
|
|
|
ASSERT(InstructionType() == kRegisterType ||
|
|
|
|
InstructionType() == kImmediateType);
|
|
|
|
return Bits(kRtShift + kRtBits - 1, kRtShift);
|
|
|
|
}
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
inline int RdValue() const {
|
2010-02-04 20:36:58 +00:00
|
|
|
ASSERT(InstructionType() == kRegisterType);
|
|
|
|
return Bits(kRdShift + kRdBits - 1, kRdShift);
|
|
|
|
}
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
inline int SaValue() const {
|
2010-02-04 20:36:58 +00:00
|
|
|
ASSERT(InstructionType() == kRegisterType);
|
|
|
|
return Bits(kSaShift + kSaBits - 1, kSaShift);
|
|
|
|
}
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
inline int FunctionValue() const {
|
2010-02-04 20:36:58 +00:00
|
|
|
ASSERT(InstructionType() == kRegisterType ||
|
|
|
|
InstructionType() == kImmediateType);
|
|
|
|
return Bits(kFunctionShift + kFunctionBits - 1, kFunctionShift);
|
|
|
|
}
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
inline int FdValue() const {
|
|
|
|
return Bits(kFdShift + kFdBits - 1, kFdShift);
|
|
|
|
}
|
|
|
|
|
|
|
|
inline int FsValue() const {
|
|
|
|
return Bits(kFsShift + kFsBits - 1, kFsShift);
|
|
|
|
}
|
|
|
|
|
|
|
|
inline int FtValue() const {
|
|
|
|
return Bits(kFtShift + kFtBits - 1, kFtShift);
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
// Float Compare condition code instruction bits.
|
|
|
|
inline int FCccValue() const {
|
|
|
|
return Bits(kFCccShift + kFCccBits - 1, kFCccShift);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Float Branch condition code instruction bits.
|
|
|
|
inline int FBccValue() const {
|
|
|
|
return Bits(kFBccShift + kFBccBits - 1, kFBccShift);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Float Branch true/false instruction bit.
|
|
|
|
inline int FBtrueValue() const {
|
|
|
|
return Bits(kFBtrueShift + kFBtrueBits - 1, kFBtrueShift);
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Return the fields at their original place in the instruction encoding.
|
|
|
|
inline Opcode OpcodeFieldRaw() const {
|
|
|
|
return static_cast<Opcode>(InstructionBits() & kOpcodeMask);
|
|
|
|
}
|
|
|
|
|
|
|
|
inline int RsFieldRaw() const {
|
|
|
|
ASSERT(InstructionType() == kRegisterType ||
|
|
|
|
InstructionType() == kImmediateType);
|
|
|
|
return InstructionBits() & kRsFieldMask;
|
|
|
|
}
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
// Same as above function, but safe to call within InstructionType().
|
|
|
|
inline int RsFieldRawNoAssert() const {
|
|
|
|
return InstructionBits() & kRsFieldMask;
|
|
|
|
}
|
|
|
|
|
2010-02-04 20:36:58 +00:00
|
|
|
inline int RtFieldRaw() const {
|
|
|
|
ASSERT(InstructionType() == kRegisterType ||
|
|
|
|
InstructionType() == kImmediateType);
|
|
|
|
return InstructionBits() & kRtFieldMask;
|
|
|
|
}
|
|
|
|
|
|
|
|
inline int RdFieldRaw() const {
|
|
|
|
ASSERT(InstructionType() == kRegisterType);
|
|
|
|
return InstructionBits() & kRdFieldMask;
|
|
|
|
}
|
|
|
|
|
|
|
|
inline int SaFieldRaw() const {
|
|
|
|
ASSERT(InstructionType() == kRegisterType);
|
|
|
|
return InstructionBits() & kSaFieldMask;
|
|
|
|
}
|
|
|
|
|
|
|
|
inline int FunctionFieldRaw() const {
|
|
|
|
return InstructionBits() & kFunctionFieldMask;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Get the secondary field according to the opcode.
|
2011-03-28 13:05:36 +00:00
|
|
|
inline int SecondaryValue() const {
|
2010-02-04 20:36:58 +00:00
|
|
|
Opcode op = OpcodeFieldRaw();
|
|
|
|
switch (op) {
|
|
|
|
case SPECIAL:
|
|
|
|
case SPECIAL2:
|
2011-03-28 13:05:36 +00:00
|
|
|
return FunctionValue();
|
2010-02-04 20:36:58 +00:00
|
|
|
case COP1:
|
2011-03-28 13:05:36 +00:00
|
|
|
return RsValue();
|
2010-02-04 20:36:58 +00:00
|
|
|
case REGIMM:
|
2011-03-28 13:05:36 +00:00
|
|
|
return RtValue();
|
2010-02-04 20:36:58 +00:00
|
|
|
default:
|
|
|
|
return NULLSF;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
inline int32_t Imm16Value() const {
|
2010-02-04 20:36:58 +00:00
|
|
|
ASSERT(InstructionType() == kImmediateType);
|
|
|
|
return Bits(kImm16Shift + kImm16Bits - 1, kImm16Shift);
|
|
|
|
}
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
inline int32_t Imm26Value() const {
|
2010-02-04 20:36:58 +00:00
|
|
|
ASSERT(InstructionType() == kJumpType);
|
2011-09-13 12:12:25 +00:00
|
|
|
return Bits(kImm26Shift + kImm26Bits - 1, kImm26Shift);
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Say if the instruction should not be used in a branch delay slot.
|
2011-03-28 13:05:36 +00:00
|
|
|
bool IsForbiddenInBranchDelay() const;
|
2012-01-16 12:38:59 +00:00
|
|
|
// Say if the instruction 'links'. e.g. jal, bal.
|
2011-03-28 13:05:36 +00:00
|
|
|
bool IsLinkingInstruction() const;
|
2010-02-04 20:36:58 +00:00
|
|
|
// Say if the instruction is a break or a trap.
|
2011-03-28 13:05:36 +00:00
|
|
|
bool IsTrap() const;
|
2010-02-04 20:36:58 +00:00
|
|
|
|
|
|
|
// Instructions are read of out a code stream. The only way to get a
|
|
|
|
// reference to an instruction is to convert a pointer. There is no way
|
|
|
|
// to allocate or create instances of class Instruction.
|
|
|
|
// Use the At(pc) function to create references to Instruction.
|
2011-05-09 14:28:09 +00:00
|
|
|
static Instruction* At(byte* pc) {
|
2010-02-04 20:36:58 +00:00
|
|
|
return reinterpret_cast<Instruction*>(pc);
|
|
|
|
}
|
|
|
|
|
|
|
|
private:
|
|
|
|
// We need to prevent the creation of instances of class Instruction.
|
|
|
|
DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction);
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
// -----------------------------------------------------------------------------
|
|
|
|
// MIPS assembly various constants.
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
// C/C++ argument slots size.
|
2011-11-29 10:56:11 +00:00
|
|
|
const int kCArgSlotCount = 4;
|
|
|
|
const int kCArgsSlotsSize = kCArgSlotCount * Instruction::kInstrSize;
|
2011-03-28 13:05:36 +00:00
|
|
|
// JS argument slots size.
|
2011-11-29 10:56:11 +00:00
|
|
|
const int kJSArgsSlotsSize = 0 * Instruction::kInstrSize;
|
2011-03-28 13:05:36 +00:00
|
|
|
// Assembly builtins argument slots size.
|
2011-11-29 10:56:11 +00:00
|
|
|
const int kBArgsSlotsSize = 0 * Instruction::kInstrSize;
|
2010-02-04 20:36:58 +00:00
|
|
|
|
2011-11-29 10:56:11 +00:00
|
|
|
const int kBranchReturnOffset = 2 * Instruction::kInstrSize;
|
2010-02-04 20:36:58 +00:00
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
} } // namespace v8::internal
|
2010-02-04 20:36:58 +00:00
|
|
|
|
|
|
|
#endif // #ifndef V8_MIPS_CONSTANTS_H_
|