2008-09-09 20:08:45 +00:00
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// Copyright 2007-2008 the V8 project authors. All rights reserved.
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2008-07-03 15:10:15 +00:00
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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// * Neither the name of Google Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#include <assert.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#ifndef WIN32
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#include <stdint.h>
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#endif
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#include "v8.h"
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#include "disasm.h"
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#include "macro-assembler.h"
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#include "platform.h"
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namespace assembler { namespace arm {
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namespace v8i = v8::internal;
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//------------------------------------------------------------------------------
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// Decoder decodes and disassembles instructions into an output buffer.
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// It uses the converter to convert register names and call destinations into
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// more informative description.
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class Decoder {
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public:
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Decoder(const disasm::NameConverter& converter,
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2008-09-11 16:41:19 +00:00
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v8::internal::Vector<char> out_buffer)
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2008-07-03 15:10:15 +00:00
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: converter_(converter),
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out_buffer_(out_buffer),
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out_buffer_pos_(0) {
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out_buffer_[out_buffer_pos_] = '\0';
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}
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~Decoder() {}
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// Writes one disassembled instruction into 'buffer' (0-terminated).
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// Returns the length of the disassembled machine instruction in bytes.
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int InstructionDecode(byte* instruction);
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private:
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const disasm::NameConverter& converter_;
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2008-09-11 16:41:19 +00:00
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v8::internal::Vector<char> out_buffer_;
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2008-07-03 15:10:15 +00:00
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int out_buffer_pos_;
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void PrintChar(const char ch);
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void Print(const char* str);
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void PrintRegister(int reg);
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void PrintCondition(Instr* instr);
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void PrintShiftRm(Instr* instr);
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void PrintShiftImm(Instr* instr);
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int FormatOption(Instr* instr, const char* option);
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void Format(Instr* instr, const char* format);
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void Unknown(Instr* instr);
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void DecodeType0(Instr* instr);
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void DecodeType1(Instr* instr);
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void DecodeType2(Instr* instr);
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void DecodeType3(Instr* instr);
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void DecodeType4(Instr* instr);
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void DecodeType5(Instr* instr);
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void DecodeType6(Instr* instr);
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void DecodeType7(Instr* instr);
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};
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// Append the ch to the output buffer.
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void Decoder::PrintChar(const char ch) {
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out_buffer_[out_buffer_pos_++] = ch;
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}
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// Append the str to the output buffer.
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void Decoder::Print(const char* str) {
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char cur = *str++;
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2008-09-11 16:41:19 +00:00
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while (cur != 0 && (out_buffer_pos_ < (out_buffer_.length()-1))) {
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2008-07-03 15:10:15 +00:00
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PrintChar(cur);
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cur = *str++;
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}
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out_buffer_[out_buffer_pos_] = 0;
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}
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static const char* cond_names[16] = {
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"eq", "ne", "cs" , "cc" , "mi" , "pl" , "vs" , "vc" ,
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"hi", "ls", "ge", "lt", "gt", "le", "", "invalid",
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};
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// Print the condition guarding the instruction.
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void Decoder::PrintCondition(Instr* instr) {
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Print(cond_names[instr->ConditionField()]);
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}
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// Print the register name according to the active name converter.
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void Decoder::PrintRegister(int reg) {
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Print(converter_.NameOfCPURegister(reg));
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}
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static const char* shift_names[4] = {
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"lsl", "lsr", "asr", "ror"
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};
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// Print the register shift operands for the instruction. Generally used for
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// data processing instructions.
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void Decoder::PrintShiftRm(Instr* instr) {
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Shift shift = instr->ShiftField();
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int shift_amount = instr->ShiftAmountField();
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int rm = instr->RmField();
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PrintRegister(rm);
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2008-07-30 08:49:36 +00:00
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if ((instr->RegShiftField() == 0) && (shift == LSL) && (shift_amount == 0)) {
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// Special case for using rm only.
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return;
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}
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if (instr->RegShiftField() == 0) {
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// by immediate
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if ((shift == ROR) && (shift_amount == 0)) {
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Print(", RRX");
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return;
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} else if (((shift == LSR) || (shift == ASR)) && (shift_amount == 0)) {
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shift_amount = 32;
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2008-07-03 15:10:15 +00:00
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}
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2008-07-30 08:49:36 +00:00
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out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
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", %s #%d",
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shift_names[shift], shift_amount);
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} else {
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// by register
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int rs = instr->RsField();
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out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
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", %s ", shift_names[shift]);
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PrintRegister(rs);
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2008-07-03 15:10:15 +00:00
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}
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}
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// Print the immediate operand for the instruction. Generally used for data
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// processing instructions.
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void Decoder::PrintShiftImm(Instr* instr) {
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int rotate = instr->RotateField() * 2;
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int immed8 = instr->Immed8Field();
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int imm = (immed8 >> rotate) | (immed8 << (32 - rotate));
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out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
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"#%d", imm);
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}
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// FormatOption takes a formatting string and interprets it based on
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// the current instructions. The format string points to the first
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// character of the option string (the option escape has already been
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// consumed by the caller.) FormatOption returns the number of
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// characters that were consumed from the formatting string.
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int Decoder::FormatOption(Instr* instr, const char* format) {
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switch (format[0]) {
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case 'a': { // 'a: accumulate multiplies
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if (instr->Bit(21) == 0) {
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Print("ul");
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} else {
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Print("la");
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}
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return 1;
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break;
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}
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case 'b': { // 'b: byte loads or stores
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if (instr->HasB()) {
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Print("b");
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}
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return 1;
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break;
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}
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case 'c': { // 'cond: conditional execution
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ASSERT((format[1] == 'o') && (format[2] == 'n') && (format[3] =='d'));
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PrintCondition(instr);
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return 4;
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break;
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}
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case 'h': { // 'h: halfword operation for extra loads and stores
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if (instr->HasH()) {
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Print("h");
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} else {
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Print("b");
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}
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return 1;
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break;
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}
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case 'i': { // 'imm: immediate value for data processing instructions
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ASSERT((format[1] == 'm') && (format[2] == 'm'));
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PrintShiftImm(instr);
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return 3;
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break;
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}
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case 'l': { // 'l: branch and link
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if (instr->HasLink()) {
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Print("l");
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}
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return 1;
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break;
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}
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case 'm': { // 'msg: for simulator break instructions
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if (format[1] == 'e') {
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ASSERT((format[2] == 'm') && (format[3] == 'o') && (format[4] == 'p'));
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if (instr->HasL()) {
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Print("ldr");
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} else {
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Print("str");
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}
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return 5;
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} else {
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ASSERT(format[1] == 's' && format[2] == 'g');
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byte* str =
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reinterpret_cast<byte*>(instr->InstructionBits() & 0x0fffffff);
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out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
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"%s", converter_.NameInCode(str));
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return 3;
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}
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break;
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}
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case 'o': {
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ASSERT(format[1] == 'f' && format[2] == 'f');
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if (format[3] == '1') {
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// 'off12: 12-bit offset for load and store instructions
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ASSERT(format[4] == '2');
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out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
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"%d", instr->Offset12Field());
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return 5;
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} else {
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// 'off8: 8-bit offset for extra load and store instructions
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ASSERT(format[3] == '8');
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int offs8 = (instr->ImmedHField() << 4) | instr->ImmedLField();
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out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
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"%d", offs8);
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return 4;
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}
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break;
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}
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2008-09-01 09:16:49 +00:00
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case 'p': { // 'pu: P and U bits for load and store instructions
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2008-07-03 15:10:15 +00:00
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ASSERT(format[1] == 'u');
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switch (instr->PUField()) {
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case 0: {
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Print("da");
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break;
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}
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case 1: {
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Print("ia");
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break;
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}
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case 2: {
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Print("db");
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break;
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}
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case 3: {
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Print("ib");
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break;
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}
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default: {
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UNREACHABLE();
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break;
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}
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}
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return 2;
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break;
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}
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case 'r': {
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if (format[1] == 'n') { // 'rn: Rn register
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int reg = instr->RnField();
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PrintRegister(reg);
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return 2;
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} else if (format[1] == 'd') { // 'rd: Rd register
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int reg = instr->RdField();
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PrintRegister(reg);
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return 2;
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} else if (format[1] == 's') { // 'rs: Rs register
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int reg = instr->RsField();
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PrintRegister(reg);
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return 2;
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} else if (format[1] == 'm') { // 'rm: Rm register
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int reg = instr->RmField();
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PrintRegister(reg);
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return 2;
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} else if (format[1] == 'l') {
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// 'rlist: register list for load and store multiple instructions
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ASSERT(format[2] == 'i' && format[3] == 's' && format[4] == 't');
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int rlist = instr->RlistField();
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int reg = 0;
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Print("{");
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while (rlist != 0) {
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if ((rlist & 1) != 0) {
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PrintRegister(reg);
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if ((rlist >> 1) != 0) {
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Print(", ");
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}
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}
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reg++;
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rlist >>= 1;
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}
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Print("}");
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return 5;
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} else {
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UNREACHABLE();
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}
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UNREACHABLE();
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return -1;
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break;
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}
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case 's': {
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if (format[1] == 'h') { // 'shift_rm: register shift operands
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ASSERT(format[2] == 'i' && format[3] == 'f' && format[4] == 't'
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&& format[5] == '_' && format[6] == 'r' && format[7] == 'm');
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PrintShiftRm(instr);
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return 8;
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} else if (format[1] == 'w') {
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ASSERT(format[2] == 'i');
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SoftwareInterruptCodes swi = instr->SwiField();
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switch (swi) {
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case call_rt_r5:
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Print("call_rt_r5");
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break;
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case call_rt_r2:
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Print("call_rt_r2");
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break;
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case break_point:
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Print("break_point");
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break;
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default:
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out_buffer_pos_ += v8i::OS::SNPrintF(
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out_buffer_ + out_buffer_pos_,
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"%d",
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swi);
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break;
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}
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return 3;
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} else if (format[1] == 'i') { // 'sign: signed extra loads and stores
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ASSERT(format[2] == 'g' && format[3] == 'n');
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if (instr->HasSign()) {
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Print("s");
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}
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return 4;
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break;
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} else { // 's: S field of data processing instructions
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if (instr->HasS()) {
|
|
|
|
Print("s");
|
|
|
|
}
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 't': { // 'target: target of branch instructions
|
|
|
|
ASSERT(format[1] == 'a' && format[2] == 'r' && format[3] == 'g'
|
|
|
|
&& format[4] == 'e' && format[5] == 't');
|
|
|
|
int off = (instr->SImmed24Field() << 2) + 8;
|
|
|
|
out_buffer_pos_ += v8i::OS::SNPrintF(
|
|
|
|
out_buffer_ + out_buffer_pos_,
|
|
|
|
"%+d -> %s",
|
|
|
|
off,
|
|
|
|
converter_.NameOfAddress(reinterpret_cast<byte*>(instr) + off));
|
|
|
|
return 6;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 'u': { // 'u: signed or unsigned multiplies
|
|
|
|
if (instr->Bit(22) == 0) {
|
|
|
|
Print("u");
|
|
|
|
} else {
|
|
|
|
Print("s");
|
|
|
|
}
|
|
|
|
return 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 'w': { // 'w: W field of load and store instructions
|
|
|
|
if (instr->HasW()) {
|
|
|
|
Print("!");
|
|
|
|
}
|
|
|
|
return 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
default: {
|
|
|
|
UNREACHABLE();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
UNREACHABLE();
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// Format takes a formatting string for a whole instruction and prints it into
|
|
|
|
// the output buffer. All escaped options are handed to FormatOption to be
|
|
|
|
// parsed further.
|
|
|
|
void Decoder::Format(Instr* instr, const char* format) {
|
|
|
|
char cur = *format++;
|
2008-09-11 16:41:19 +00:00
|
|
|
while ((cur != 0) && (out_buffer_pos_ < (out_buffer_.length() - 1))) {
|
2008-07-03 15:10:15 +00:00
|
|
|
if (cur == '\'') { // Single quote is used as the formatting escape.
|
|
|
|
format += FormatOption(instr, format);
|
|
|
|
} else {
|
|
|
|
out_buffer_[out_buffer_pos_++] = cur;
|
|
|
|
}
|
|
|
|
cur = *format++;
|
|
|
|
}
|
|
|
|
out_buffer_[out_buffer_pos_] = '\0';
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// For currently unimplemented decodings the disassembler calls Unknown(instr)
|
|
|
|
// which will just print "unknown" of the instruction bits.
|
|
|
|
void Decoder::Unknown(Instr* instr) {
|
|
|
|
Format(instr, "unknown");
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Decoder::DecodeType0(Instr* instr) {
|
|
|
|
if (instr->IsSpecialType0()) {
|
|
|
|
// multiply instruction or extra loads and stores
|
|
|
|
if (instr->Bits(7, 4) == 9) {
|
|
|
|
if (instr->Bit(24) == 0) {
|
|
|
|
// multiply instructions
|
|
|
|
if (instr->Bit(23) == 0) {
|
|
|
|
if (instr->Bit(21) == 0) {
|
|
|
|
Format(instr, "mul'cond's 'rd, 'rm, 'rs");
|
|
|
|
} else {
|
|
|
|
Format(instr, "mla'cond's 'rd, 'rm, 'rs, 'rn");
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
Format(instr, "'um'al'cond's 'rn, 'rd, 'rs, 'rm");
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
Unknown(instr); // not used by V8
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
// extra load/store instructions
|
|
|
|
switch (instr->PUField()) {
|
|
|
|
case 0: {
|
|
|
|
if (instr->Bit(22) == 0) {
|
|
|
|
Format(instr, "'memop'cond'sign'h 'rd, ['rn], -'rm");
|
|
|
|
} else {
|
|
|
|
Format(instr, "'memop'cond'sign'h 'rd, ['rn], #-'off8");
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 1: {
|
|
|
|
if (instr->Bit(22) == 0) {
|
|
|
|
Format(instr, "'memop'cond'sign'h 'rd, ['rn], +'rm");
|
|
|
|
} else {
|
|
|
|
Format(instr, "'memop'cond'sign'h 'rd, ['rn], #+'off8");
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 2: {
|
|
|
|
if (instr->Bit(22) == 0) {
|
|
|
|
Format(instr, "'memop'cond'sign'h 'rd, ['rn, -'rm]'w");
|
|
|
|
} else {
|
|
|
|
Format(instr, "'memop'cond'sign'h 'rd, ['rn, #-'off8]'w");
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 3: {
|
|
|
|
if (instr->Bit(22) == 0) {
|
|
|
|
Format(instr, "'memop'cond'sign'h 'rd, ['rn, +'rm]'w");
|
|
|
|
} else {
|
|
|
|
Format(instr, "'memop'cond'sign'h 'rd, ['rn, #+'off8]'w");
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
default: {
|
|
|
|
// The PU field is a 2-bit field.
|
|
|
|
UNREACHABLE();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
switch (instr->OpcodeField()) {
|
|
|
|
case AND: {
|
|
|
|
Format(instr, "and'cond's 'rd, 'rn, 'shift_rm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case EOR: {
|
|
|
|
Format(instr, "eor'cond's 'rd, 'rn, 'shift_rm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case SUB: {
|
|
|
|
Format(instr, "sub'cond's 'rd, 'rn, 'shift_rm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case RSB: {
|
|
|
|
Format(instr, "rsb'cond's 'rd, 'rn, 'shift_rm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ADD: {
|
|
|
|
Format(instr, "add'cond's 'rd, 'rn, 'shift_rm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ADC: {
|
|
|
|
Format(instr, "adc'cond's 'rd, 'rn, 'shift_rm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case SBC: {
|
|
|
|
Format(instr, "sbc'cond's 'rd, 'rn, 'shift_rm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case RSC: {
|
|
|
|
Format(instr, "rsc'cond's 'rd, 'rn, 'shift_rm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case TST: {
|
|
|
|
if (instr->HasS()) {
|
|
|
|
Format(instr, "tst'cond 'rn, 'shift_rm");
|
|
|
|
} else {
|
|
|
|
Unknown(instr); // not used by V8
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case TEQ: {
|
|
|
|
if (instr->HasS()) {
|
|
|
|
Format(instr, "teq'cond 'rn, 'shift_rm");
|
|
|
|
} else {
|
|
|
|
Unknown(instr); // not used by V8
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case CMP: {
|
|
|
|
if (instr->HasS()) {
|
|
|
|
Format(instr, "cmp'cond 'rn, 'shift_rm");
|
|
|
|
} else {
|
|
|
|
Unknown(instr); // not used by V8
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case CMN: {
|
|
|
|
if (instr->HasS()) {
|
|
|
|
Format(instr, "cmn'cond 'rn, 'shift_rm");
|
|
|
|
} else {
|
|
|
|
Unknown(instr); // not used by V8
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ORR: {
|
|
|
|
Format(instr, "orr'cond's 'rd, 'rn, 'shift_rm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case MOV: {
|
|
|
|
Format(instr, "mov'cond's 'rd, 'shift_rm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case BIC: {
|
|
|
|
Format(instr, "bic'cond's 'rd, 'rn, 'shift_rm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case MVN: {
|
|
|
|
Format(instr, "mvn'cond's 'rd, 'shift_rm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
default: {
|
|
|
|
// The Opcode field is a 4-bit field.
|
|
|
|
UNREACHABLE();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Decoder::DecodeType1(Instr* instr) {
|
|
|
|
switch (instr->OpcodeField()) {
|
|
|
|
case AND: {
|
|
|
|
Format(instr, "and'cond's 'rd, 'rn, 'imm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case EOR: {
|
|
|
|
Format(instr, "eor'cond's 'rd, 'rn, 'imm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case SUB: {
|
|
|
|
Format(instr, "sub'cond's 'rd, 'rn, 'imm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case RSB: {
|
|
|
|
Format(instr, "rsb'cond's 'rd, 'rn, 'imm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ADD: {
|
|
|
|
Format(instr, "add'cond's 'rd, 'rn, 'imm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ADC: {
|
|
|
|
Format(instr, "adc'cond's 'rd, 'rn, 'imm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case SBC: {
|
|
|
|
Format(instr, "sbc'cond's 'rd, 'rn, 'imm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case RSC: {
|
|
|
|
Format(instr, "rsc'cond's 'rd, 'rn, 'imm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case TST: {
|
|
|
|
if (instr->HasS()) {
|
|
|
|
Format(instr, "tst'cond 'rn, 'imm");
|
|
|
|
} else {
|
|
|
|
Unknown(instr); // not used by V8
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case TEQ: {
|
|
|
|
if (instr->HasS()) {
|
|
|
|
Format(instr, "teq'cond 'rn, 'imm");
|
|
|
|
} else {
|
|
|
|
Unknown(instr); // not used by V8
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case CMP: {
|
|
|
|
if (instr->HasS()) {
|
|
|
|
Format(instr, "cmp'cond 'rn, 'imm");
|
|
|
|
} else {
|
|
|
|
Unknown(instr); // not used by V8
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case CMN: {
|
|
|
|
if (instr->HasS()) {
|
|
|
|
Format(instr, "cmn'cond 'rn, 'imm");
|
|
|
|
} else {
|
|
|
|
Unknown(instr); // not used by V8
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ORR: {
|
|
|
|
Format(instr, "orr'cond's 'rd, 'rn, 'imm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case MOV: {
|
|
|
|
Format(instr, "mov'cond's 'rd, 'imm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case BIC: {
|
|
|
|
Format(instr, "bic'cond's 'rd, 'rn, 'imm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case MVN: {
|
|
|
|
Format(instr, "mvn'cond's 'rd, 'imm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
default: {
|
|
|
|
// The Opcode field is a 4-bit field.
|
|
|
|
UNREACHABLE();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Decoder::DecodeType2(Instr* instr) {
|
|
|
|
switch (instr->PUField()) {
|
|
|
|
case 0: {
|
|
|
|
if (instr->HasW()) {
|
|
|
|
Unknown(instr); // not used in V8
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
Format(instr, "'memop'cond'b 'rd, ['rn], #-'off12");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 1: {
|
|
|
|
if (instr->HasW()) {
|
|
|
|
Unknown(instr); // not used in V8
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
Format(instr, "'memop'cond'b 'rd, ['rn], #+'off12");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 2: {
|
|
|
|
Format(instr, "'memop'cond'b 'rd, ['rn, #-'off12]'w");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 3: {
|
|
|
|
Format(instr, "'memop'cond'b 'rd, ['rn, #+'off12]'w");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
default: {
|
|
|
|
// The PU field is a 2-bit field.
|
|
|
|
UNREACHABLE();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Decoder::DecodeType3(Instr* instr) {
|
|
|
|
switch (instr->PUField()) {
|
|
|
|
case 0: {
|
|
|
|
ASSERT(!instr->HasW());
|
|
|
|
Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 1: {
|
|
|
|
ASSERT(!instr->HasW());
|
|
|
|
Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 2: {
|
|
|
|
Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 3: {
|
|
|
|
Format(instr, "'memop'cond'b 'rd, ['rn, +'shift_rm]'w");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
default: {
|
|
|
|
// The PU field is a 2-bit field.
|
|
|
|
UNREACHABLE();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Decoder::DecodeType4(Instr* instr) {
|
|
|
|
ASSERT(instr->Bit(22) == 0); // Privileged mode currently not supported.
|
|
|
|
if (instr->HasL()) {
|
|
|
|
Format(instr, "ldm'cond'pu 'rn'w, 'rlist");
|
|
|
|
} else {
|
|
|
|
Format(instr, "stm'cond'pu 'rn'w, 'rlist");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Decoder::DecodeType5(Instr* instr) {
|
|
|
|
Format(instr, "b'l'cond 'target");
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Decoder::DecodeType6(Instr* instr) {
|
|
|
|
// Coprocessor instructions currently not supported.
|
|
|
|
Unknown(instr);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Decoder::DecodeType7(Instr* instr) {
|
|
|
|
if (instr->Bit(24) == 1) {
|
|
|
|
Format(instr, "swi'cond 'swi");
|
|
|
|
} else {
|
|
|
|
// Coprocessor instructions currently not supported.
|
|
|
|
Unknown(instr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// Disassemble the instruction at *instr_ptr into the output buffer.
|
|
|
|
int Decoder::InstructionDecode(byte* instr_ptr) {
|
|
|
|
Instr* instr = Instr::At(instr_ptr);
|
2008-07-30 08:49:36 +00:00
|
|
|
// Print raw instruction bytes.
|
|
|
|
out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
|
|
|
|
"%08x ",
|
|
|
|
instr->InstructionBits());
|
2008-07-03 15:10:15 +00:00
|
|
|
if (instr->ConditionField() == special_condition) {
|
|
|
|
Format(instr, "break 'msg");
|
|
|
|
return Instr::kInstrSize;
|
|
|
|
}
|
|
|
|
switch (instr->TypeField()) {
|
|
|
|
case 0: {
|
|
|
|
DecodeType0(instr);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 1: {
|
|
|
|
DecodeType1(instr);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 2: {
|
|
|
|
DecodeType2(instr);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 3: {
|
|
|
|
DecodeType3(instr);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 4: {
|
|
|
|
DecodeType4(instr);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 5: {
|
|
|
|
DecodeType5(instr);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 6: {
|
|
|
|
DecodeType6(instr);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 7: {
|
|
|
|
DecodeType7(instr);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
default: {
|
|
|
|
// The type field is 3-bits in the ARM encoding.
|
|
|
|
UNREACHABLE();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return Instr::kInstrSize;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
} } // namespace assembler::arm
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
namespace disasm {
|
|
|
|
|
|
|
|
static const char* reg_names[16] = {
|
|
|
|
"r0", "r1", "r2" , "r3" , "r4" , "r5" , "r6" , "r7" ,
|
|
|
|
"r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc",
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
const char* NameConverter::NameOfAddress(byte* addr) const {
|
|
|
|
static char tmp_buffer[32];
|
|
|
|
#ifdef WIN32
|
|
|
|
_snprintf(tmp_buffer, sizeof tmp_buffer, "%p", addr);
|
|
|
|
#else
|
|
|
|
snprintf(tmp_buffer, sizeof tmp_buffer, "%p", addr);
|
|
|
|
#endif
|
|
|
|
return tmp_buffer;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
const char* NameConverter::NameOfConstant(byte* addr) const {
|
|
|
|
return NameOfAddress(addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
const char* NameConverter::NameOfCPURegister(int reg) const {
|
|
|
|
const char* result;
|
|
|
|
if ((0 <= reg) && (reg < 16)) {
|
|
|
|
result = reg_names[reg];
|
|
|
|
} else {
|
|
|
|
result = "noreg";
|
|
|
|
}
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
const char* NameConverter::NameOfXMMRegister(int reg) const {
|
|
|
|
UNREACHABLE(); // ARM does not have any XMM registers
|
|
|
|
return "noxmmreg";
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
const char* NameConverter::NameInCode(byte* addr) const {
|
|
|
|
// The default name converter is called for unknown code. So we will not try
|
|
|
|
// to access any memory.
|
|
|
|
return "";
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
//------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
static NameConverter defaultConverter;
|
|
|
|
|
|
|
|
Disassembler::Disassembler() : converter_(defaultConverter) {}
|
|
|
|
|
|
|
|
|
|
|
|
Disassembler::Disassembler(const NameConverter& converter)
|
|
|
|
: converter_(converter) {}
|
|
|
|
|
|
|
|
|
|
|
|
Disassembler::~Disassembler() {}
|
|
|
|
|
|
|
|
|
2008-09-11 16:41:19 +00:00
|
|
|
int Disassembler::InstructionDecode(v8::internal::Vector<char> buffer,
|
2008-07-03 15:10:15 +00:00
|
|
|
byte* instruction) {
|
2008-09-11 16:41:19 +00:00
|
|
|
assembler::arm::Decoder d(converter_, buffer);
|
2008-07-03 15:10:15 +00:00
|
|
|
return d.InstructionDecode(instruction);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2008-07-30 08:49:36 +00:00
|
|
|
int Disassembler::ConstantPoolSizeAt(byte* instruction) {
|
|
|
|
int instruction_bits = *(reinterpret_cast<int*>(instruction));
|
|
|
|
if ((instruction_bits & 0xfff00000) == 0x03000000) {
|
|
|
|
return instruction_bits & 0x0000ffff;
|
|
|
|
} else {
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2008-07-03 15:10:15 +00:00
|
|
|
void Disassembler::Disassemble(FILE* f, byte* begin, byte* end) {
|
|
|
|
Disassembler d;
|
|
|
|
for (byte* pc = begin; pc < end;) {
|
2008-09-11 16:41:19 +00:00
|
|
|
v8::internal::EmbeddedVector<char, 128> buffer;
|
2008-07-03 15:10:15 +00:00
|
|
|
buffer[0] = '\0';
|
|
|
|
byte* prev_pc = pc;
|
2008-09-11 16:41:19 +00:00
|
|
|
pc += d.InstructionDecode(buffer, pc);
|
2008-07-30 08:49:36 +00:00
|
|
|
fprintf(f, "%p %08x %s\n",
|
2008-09-11 16:41:19 +00:00
|
|
|
prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
|
2008-07-03 15:10:15 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
} // namespace disasm
|