Implement ldrex/strex instructions in ARM simulator
This CL implements ldrex, ldrexb, ldrexh, strex, strexb, and strexh in the
Simulator. These instructions provide "exclusive" access, which provides mutual
exclusion for concurrent threads of execution.
The ARM specification gives some leeway to implementors, but essentially
describes each processor as having Local Monitor and Global Monitor. The Local
Monitor is used to check the exclusivity state without having to synchronize
with other processors. The Global Monitor is shared between processors. We
model both to make it easier to match behavior with the spec.
When running with multiple OS threads, each thread has its own isolate, and
each isolate has its own Simulator. The Local Monitor is stored directly on the
Simulator, and the Global Monitor is stored as a lazy singleton. The Global
Monitor maintains a linked-list of all Simulators.
All loads/stores (even non-exclusive) are guarded by the Global Monitor's mutex.
BUG=v8:4614
Review-Url: https://codereview.chromium.org/2006183004
Cr-Commit-Position: refs/heads/master@{#42481}
2017-01-18 22:17:46 +00:00
|
|
|
// Copyright 2016 the V8 project authors. All rights reserved.
|
|
|
|
// Redistribution and use in source and binary forms, with or without
|
|
|
|
// modification, are permitted provided that the following conditions are
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|
// met:
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|
//
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|
// * Redistributions of source code must retain the above copyright
|
|
|
|
// notice, this list of conditions and the following disclaimer.
|
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// * Redistributions in binary form must reproduce the above
|
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|
// copyright notice, this list of conditions and the following
|
|
|
|
// disclaimer in the documentation and/or other materials provided
|
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|
|
// with the distribution.
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|
// * Neither the name of Google Inc. nor the names of its
|
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// contributors may be used to endorse or promote products derived
|
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|
// from this software without specific prior written permission.
|
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
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|
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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|
|
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
|
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
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|
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#include "src/v8.h"
|
Revert "Revert "[cctest] Clarify that tests for sync instructions are simulator specific""
This reverts commit 1feadfe81b7cc250df83cbf0b2fdfd17ac348cf8.
Reason for revert: Reland as bot stayed red after revert.
Original change's description:
> Revert "[cctest] Clarify that tests for sync instructions are simulator specific"
>
> This reverts commit 4013518fe3be92f0fbd043b09017f5eb8b8629d8.
>
> Reason for revert:
> https://build.chromium.org/p/client.v8.ports/builders/V8%20Linux%20-%20arm64%20-%20sim%20-%20gc%20stress
>
> Original change's description:
> > [cctest] Clarify that tests for sync instructions are simulator specific
> >
> > Some tests were recently added to test-simulator-arm.cc, however this file is
> > meant for tests that are specific to the simulator and therefore are not written
> > to work on hardware. While this sounds surprising, the reason is that our simulation
> > of synchronisation instructions is more conservative than on hardware.
> >
> > To make this more clear, this patch renames the "test-simulator-arm{,64}.cc"
> > files to "test-sync-primitives-arm{,64}.cc", and moves the vneg and vabs tests
> > into "test-assembler-arm.cc" which is were tests that are garanteed to work in
> > either native or simulated environments live.
> >
> > Finally, take the opportunity to share a little bit of code.
> >
> > Bug: v8:6963
> > Change-Id: Ifb85d3671c823b9bba73d09f419536b089a4e87c
> > Reviewed-on: https://chromium-review.googlesource.com/749387
> > Reviewed-by: Clemens Hammacher <clemensh@chromium.org>
> > Commit-Queue: Pierre Langlois <pierre.langlois@arm.com>
> > Cr-Commit-Position: refs/heads/master@{#49073}
>
> TBR=clemensh@chromium.org,pierre.langlois@arm.com,bmeurer@chromium.org
>
> Change-Id: I1bfb4e9c7c18b716f417a84b18a14cb2e1fa3a7a
> No-Presubmit: true
> No-Tree-Checks: true
> No-Try: true
> Bug: v8:6963
> Reviewed-on: https://chromium-review.googlesource.com/750624
> Reviewed-by: Michael Achenbach <machenbach@chromium.org>
> Commit-Queue: Michael Achenbach <machenbach@chromium.org>
> Cr-Commit-Position: refs/heads/master@{#49074}
TBR=machenbach@chromium.org,clemensh@chromium.org,pierre.langlois@arm.com,bmeurer@chromium.org
Change-Id: I5af7bd3678758130534730a2f6f0b651b64c6956
No-Presubmit: true
No-Tree-Checks: true
No-Try: true
Bug: v8:6963
Reviewed-on: https://chromium-review.googlesource.com/750903
Reviewed-by: Michael Achenbach <machenbach@chromium.org>
Commit-Queue: Michael Achenbach <machenbach@chromium.org>
Cr-Commit-Position: refs/heads/master@{#49075}
2017-11-02 13:11:29 +00:00
|
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|
#include "test/cctest/assembler-helper-arm.h"
|
Implement ldrex/strex instructions in ARM simulator
This CL implements ldrex, ldrexb, ldrexh, strex, strexb, and strexh in the
Simulator. These instructions provide "exclusive" access, which provides mutual
exclusion for concurrent threads of execution.
The ARM specification gives some leeway to implementors, but essentially
describes each processor as having Local Monitor and Global Monitor. The Local
Monitor is used to check the exclusivity state without having to synchronize
with other processors. The Global Monitor is shared between processors. We
model both to make it easier to match behavior with the spec.
When running with multiple OS threads, each thread has its own isolate, and
each isolate has its own Simulator. The Local Monitor is stored directly on the
Simulator, and the Global Monitor is stored as a lazy singleton. The Global
Monitor maintains a linked-list of all Simulators.
All loads/stores (even non-exclusive) are guarded by the Global Monitor's mutex.
BUG=v8:4614
Review-Url: https://codereview.chromium.org/2006183004
Cr-Commit-Position: refs/heads/master@{#42481}
2017-01-18 22:17:46 +00:00
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#include "test/cctest/cctest.h"
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2017-09-13 10:56:20 +00:00
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#include "src/assembler-inl.h"
|
Implement ldrex/strex instructions in ARM simulator
This CL implements ldrex, ldrexb, ldrexh, strex, strexb, and strexh in the
Simulator. These instructions provide "exclusive" access, which provides mutual
exclusion for concurrent threads of execution.
The ARM specification gives some leeway to implementors, but essentially
describes each processor as having Local Monitor and Global Monitor. The Local
Monitor is used to check the exclusivity state without having to synchronize
with other processors. The Global Monitor is shared between processors. We
model both to make it easier to match behavior with the spec.
When running with multiple OS threads, each thread has its own isolate, and
each isolate has its own Simulator. The Local Monitor is stored directly on the
Simulator, and the Global Monitor is stored as a lazy singleton. The Global
Monitor maintains a linked-list of all Simulators.
All loads/stores (even non-exclusive) are guarded by the Global Monitor's mutex.
BUG=v8:4614
Review-Url: https://codereview.chromium.org/2006183004
Cr-Commit-Position: refs/heads/master@{#42481}
2017-01-18 22:17:46 +00:00
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#include "src/disassembler.h"
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#include "src/factory.h"
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#include "src/macro-assembler.h"
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2017-12-11 14:12:29 +00:00
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#include "src/simulator.h"
|
Implement ldrex/strex instructions in ARM simulator
This CL implements ldrex, ldrexb, ldrexh, strex, strexb, and strexh in the
Simulator. These instructions provide "exclusive" access, which provides mutual
exclusion for concurrent threads of execution.
The ARM specification gives some leeway to implementors, but essentially
describes each processor as having Local Monitor and Global Monitor. The Local
Monitor is used to check the exclusivity state without having to synchronize
with other processors. The Global Monitor is shared between processors. We
model both to make it easier to match behavior with the spec.
When running with multiple OS threads, each thread has its own isolate, and
each isolate has its own Simulator. The Local Monitor is stored directly on the
Simulator, and the Global Monitor is stored as a lazy singleton. The Global
Monitor maintains a linked-list of all Simulators.
All loads/stores (even non-exclusive) are guarded by the Global Monitor's mutex.
BUG=v8:4614
Review-Url: https://codereview.chromium.org/2006183004
Cr-Commit-Position: refs/heads/master@{#42481}
2017-01-18 22:17:46 +00:00
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2017-08-31 12:34:55 +00:00
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namespace v8 {
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namespace internal {
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Revert "Revert "[cctest] Clarify that tests for sync instructions are simulator specific""
This reverts commit 1feadfe81b7cc250df83cbf0b2fdfd17ac348cf8.
Reason for revert: Reland as bot stayed red after revert.
Original change's description:
> Revert "[cctest] Clarify that tests for sync instructions are simulator specific"
>
> This reverts commit 4013518fe3be92f0fbd043b09017f5eb8b8629d8.
>
> Reason for revert:
> https://build.chromium.org/p/client.v8.ports/builders/V8%20Linux%20-%20arm64%20-%20sim%20-%20gc%20stress
>
> Original change's description:
> > [cctest] Clarify that tests for sync instructions are simulator specific
> >
> > Some tests were recently added to test-simulator-arm.cc, however this file is
> > meant for tests that are specific to the simulator and therefore are not written
> > to work on hardware. While this sounds surprising, the reason is that our simulation
> > of synchronisation instructions is more conservative than on hardware.
> >
> > To make this more clear, this patch renames the "test-simulator-arm{,64}.cc"
> > files to "test-sync-primitives-arm{,64}.cc", and moves the vneg and vabs tests
> > into "test-assembler-arm.cc" which is were tests that are garanteed to work in
> > either native or simulated environments live.
> >
> > Finally, take the opportunity to share a little bit of code.
> >
> > Bug: v8:6963
> > Change-Id: Ifb85d3671c823b9bba73d09f419536b089a4e87c
> > Reviewed-on: https://chromium-review.googlesource.com/749387
> > Reviewed-by: Clemens Hammacher <clemensh@chromium.org>
> > Commit-Queue: Pierre Langlois <pierre.langlois@arm.com>
> > Cr-Commit-Position: refs/heads/master@{#49073}
>
> TBR=clemensh@chromium.org,pierre.langlois@arm.com,bmeurer@chromium.org
>
> Change-Id: I1bfb4e9c7c18b716f417a84b18a14cb2e1fa3a7a
> No-Presubmit: true
> No-Tree-Checks: true
> No-Try: true
> Bug: v8:6963
> Reviewed-on: https://chromium-review.googlesource.com/750624
> Reviewed-by: Michael Achenbach <machenbach@chromium.org>
> Commit-Queue: Michael Achenbach <machenbach@chromium.org>
> Cr-Commit-Position: refs/heads/master@{#49074}
TBR=machenbach@chromium.org,clemensh@chromium.org,pierre.langlois@arm.com,bmeurer@chromium.org
Change-Id: I5af7bd3678758130534730a2f6f0b651b64c6956
No-Presubmit: true
No-Tree-Checks: true
No-Try: true
Bug: v8:6963
Reviewed-on: https://chromium-review.googlesource.com/750903
Reviewed-by: Michael Achenbach <machenbach@chromium.org>
Commit-Queue: Michael Achenbach <machenbach@chromium.org>
Cr-Commit-Position: refs/heads/master@{#49075}
2017-11-02 13:11:29 +00:00
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// These tests rely on the behaviour specific to the simulator so we cannot
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// expect the same results on real hardware. The reason for this is that our
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// simulation of synchronisation primitives is more conservative than the
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// reality.
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// For example:
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// ldrex r1, [r2] ; Load acquire at address r2; r2 is now marked as exclusive.
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// ldr r0, [r4] ; This is a normal load, and at a different address.
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// ; However, any memory accesses can potentially clear the
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// ; exclusivity (See ARM DDI 0406C.c A3.4.5). This is unlikely
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// ; on real hardware but to be conservative, the simulator
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// ; always does it.
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// strex r3, r1, [r2] ; As a result, this will always fail in the simulator
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// ; but will likely succeed on hardware.
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#if defined(USE_SIMULATOR)
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Implement ldrex/strex instructions in ARM simulator
This CL implements ldrex, ldrexb, ldrexh, strex, strexb, and strexh in the
Simulator. These instructions provide "exclusive" access, which provides mutual
exclusion for concurrent threads of execution.
The ARM specification gives some leeway to implementors, but essentially
describes each processor as having Local Monitor and Global Monitor. The Local
Monitor is used to check the exclusivity state without having to synchronize
with other processors. The Global Monitor is shared between processors. We
model both to make it easier to match behavior with the spec.
When running with multiple OS threads, each thread has its own isolate, and
each isolate has its own Simulator. The Local Monitor is stored directly on the
Simulator, and the Global Monitor is stored as a lazy singleton. The Global
Monitor maintains a linked-list of all Simulators.
All loads/stores (even non-exclusive) are guarded by the Global Monitor's mutex.
BUG=v8:4614
Review-Url: https://codereview.chromium.org/2006183004
Cr-Commit-Position: refs/heads/master@{#42481}
2017-01-18 22:17:46 +00:00
|
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#ifndef V8_TARGET_LITTLE_ENDIAN
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#error Expected ARM to be little-endian
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#endif
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#define __ assm.
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2017-10-18 09:46:57 +00:00
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namespace {
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Implement ldrex/strex instructions in ARM simulator
This CL implements ldrex, ldrexb, ldrexh, strex, strexb, and strexh in the
Simulator. These instructions provide "exclusive" access, which provides mutual
exclusion for concurrent threads of execution.
The ARM specification gives some leeway to implementors, but essentially
describes each processor as having Local Monitor and Global Monitor. The Local
Monitor is used to check the exclusivity state without having to synchronize
with other processors. The Global Monitor is shared between processors. We
model both to make it easier to match behavior with the spec.
When running with multiple OS threads, each thread has its own isolate, and
each isolate has its own Simulator. The Local Monitor is stored directly on the
Simulator, and the Global Monitor is stored as a lazy singleton. The Global
Monitor maintains a linked-list of all Simulators.
All loads/stores (even non-exclusive) are guarded by the Global Monitor's mutex.
BUG=v8:4614
Review-Url: https://codereview.chromium.org/2006183004
Cr-Commit-Position: refs/heads/master@{#42481}
2017-01-18 22:17:46 +00:00
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struct MemoryAccess {
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enum class Kind {
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None,
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Load,
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LoadExcl,
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Store,
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StoreExcl,
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};
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enum class Size {
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Byte,
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HalfWord,
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Word,
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};
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MemoryAccess() : kind(Kind::None) {}
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MemoryAccess(Kind kind, Size size, size_t offset, int value = 0)
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: kind(kind), size(size), offset(offset), value(value) {}
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2017-02-28 03:31:39 +00:00
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Kind kind = Kind::None;
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Size size = Size::Byte;
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size_t offset = 0;
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int value = 0;
|
Implement ldrex/strex instructions in ARM simulator
This CL implements ldrex, ldrexb, ldrexh, strex, strexb, and strexh in the
Simulator. These instructions provide "exclusive" access, which provides mutual
exclusion for concurrent threads of execution.
The ARM specification gives some leeway to implementors, but essentially
describes each processor as having Local Monitor and Global Monitor. The Local
Monitor is used to check the exclusivity state without having to synchronize
with other processors. The Global Monitor is shared between processors. We
model both to make it easier to match behavior with the spec.
When running with multiple OS threads, each thread has its own isolate, and
each isolate has its own Simulator. The Local Monitor is stored directly on the
Simulator, and the Global Monitor is stored as a lazy singleton. The Global
Monitor maintains a linked-list of all Simulators.
All loads/stores (even non-exclusive) are guarded by the Global Monitor's mutex.
BUG=v8:4614
Review-Url: https://codereview.chromium.org/2006183004
Cr-Commit-Position: refs/heads/master@{#42481}
2017-01-18 22:17:46 +00:00
|
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};
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struct TestData {
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explicit TestData(int w) : w(w) {}
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union {
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int32_t w;
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int16_t h;
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int8_t b;
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};
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int dummy;
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};
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2017-10-18 09:46:57 +00:00
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void AssembleMemoryAccess(Assembler* assembler, MemoryAccess access,
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Register dest_reg, Register value_reg,
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Register addr_reg) {
|
Implement ldrex/strex instructions in ARM simulator
This CL implements ldrex, ldrexb, ldrexh, strex, strexb, and strexh in the
Simulator. These instructions provide "exclusive" access, which provides mutual
exclusion for concurrent threads of execution.
The ARM specification gives some leeway to implementors, but essentially
describes each processor as having Local Monitor and Global Monitor. The Local
Monitor is used to check the exclusivity state without having to synchronize
with other processors. The Global Monitor is shared between processors. We
model both to make it easier to match behavior with the spec.
When running with multiple OS threads, each thread has its own isolate, and
each isolate has its own Simulator. The Local Monitor is stored directly on the
Simulator, and the Global Monitor is stored as a lazy singleton. The Global
Monitor maintains a linked-list of all Simulators.
All loads/stores (even non-exclusive) are guarded by the Global Monitor's mutex.
BUG=v8:4614
Review-Url: https://codereview.chromium.org/2006183004
Cr-Commit-Position: refs/heads/master@{#42481}
2017-01-18 22:17:46 +00:00
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Assembler& assm = *assembler;
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__ add(addr_reg, r0, Operand(access.offset));
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switch (access.kind) {
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case MemoryAccess::Kind::None:
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break;
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case MemoryAccess::Kind::Load:
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switch (access.size) {
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case MemoryAccess::Size::Byte:
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__ ldrb(value_reg, MemOperand(addr_reg));
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break;
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case MemoryAccess::Size::HalfWord:
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__ ldrh(value_reg, MemOperand(addr_reg));
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break;
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case MemoryAccess::Size::Word:
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__ ldr(value_reg, MemOperand(addr_reg));
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break;
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}
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break;
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case MemoryAccess::Kind::LoadExcl:
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switch (access.size) {
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case MemoryAccess::Size::Byte:
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__ ldrexb(value_reg, addr_reg);
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break;
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case MemoryAccess::Size::HalfWord:
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__ ldrexh(value_reg, addr_reg);
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break;
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case MemoryAccess::Size::Word:
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__ ldrex(value_reg, addr_reg);
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break;
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}
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break;
|
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case MemoryAccess::Kind::Store:
|
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switch (access.size) {
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case MemoryAccess::Size::Byte:
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__ mov(value_reg, Operand(access.value));
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__ strb(value_reg, MemOperand(addr_reg));
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break;
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case MemoryAccess::Size::HalfWord:
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__ mov(value_reg, Operand(access.value));
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__ strh(value_reg, MemOperand(addr_reg));
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break;
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case MemoryAccess::Size::Word:
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__ mov(value_reg, Operand(access.value));
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__ str(value_reg, MemOperand(addr_reg));
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break;
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}
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break;
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case MemoryAccess::Kind::StoreExcl:
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switch (access.size) {
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case MemoryAccess::Size::Byte:
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__ mov(value_reg, Operand(access.value));
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__ strexb(dest_reg, value_reg, addr_reg);
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break;
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case MemoryAccess::Size::HalfWord:
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__ mov(value_reg, Operand(access.value));
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__ strexh(dest_reg, value_reg, addr_reg);
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|
break;
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case MemoryAccess::Size::Word:
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__ mov(value_reg, Operand(access.value));
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|
|
__ strex(dest_reg, value_reg, addr_reg);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-10-19 09:14:34 +00:00
|
|
|
void AssembleLoadExcl(Assembler* assembler, MemoryAccess access,
|
|
|
|
Register value_reg, Register addr_reg) {
|
|
|
|
DCHECK(access.kind == MemoryAccess::Kind::LoadExcl);
|
|
|
|
AssembleMemoryAccess(assembler, access, no_reg, value_reg, addr_reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
void AssembleStoreExcl(Assembler* assembler, MemoryAccess access,
|
|
|
|
Register dest_reg, Register value_reg,
|
|
|
|
Register addr_reg) {
|
|
|
|
DCHECK(access.kind == MemoryAccess::Kind::StoreExcl);
|
|
|
|
AssembleMemoryAccess(assembler, access, dest_reg, value_reg, addr_reg);
|
2017-10-19 12:09:23 +00:00
|
|
|
}
|
|
|
|
|
2017-10-18 09:46:57 +00:00
|
|
|
void TestInvalidateExclusiveAccess(TestData initial_data, MemoryAccess access1,
|
|
|
|
MemoryAccess access2, MemoryAccess access3,
|
|
|
|
int expected_res, TestData expected_data) {
|
|
|
|
Isolate* isolate = CcTest::i_isolate();
|
|
|
|
HandleScope scope(isolate);
|
|
|
|
|
2017-10-19 09:14:34 +00:00
|
|
|
F_piiii f = FUNCTION_CAST<F_piiii>(AssembleCode([&](Assembler& assm) {
|
2017-10-18 09:46:57 +00:00
|
|
|
AssembleLoadExcl(&assm, access1, r1, r1);
|
|
|
|
AssembleMemoryAccess(&assm, access2, r3, r2, r1);
|
|
|
|
AssembleStoreExcl(&assm, access3, r0, r3, r1);
|
2017-10-19 09:14:34 +00:00
|
|
|
}));
|
2017-10-18 09:46:57 +00:00
|
|
|
|
Implement ldrex/strex instructions in ARM simulator
This CL implements ldrex, ldrexb, ldrexh, strex, strexb, and strexh in the
Simulator. These instructions provide "exclusive" access, which provides mutual
exclusion for concurrent threads of execution.
The ARM specification gives some leeway to implementors, but essentially
describes each processor as having Local Monitor and Global Monitor. The Local
Monitor is used to check the exclusivity state without having to synchronize
with other processors. The Global Monitor is shared between processors. We
model both to make it easier to match behavior with the spec.
When running with multiple OS threads, each thread has its own isolate, and
each isolate has its own Simulator. The Local Monitor is stored directly on the
Simulator, and the Global Monitor is stored as a lazy singleton. The Global
Monitor maintains a linked-list of all Simulators.
All loads/stores (even non-exclusive) are guarded by the Global Monitor's mutex.
BUG=v8:4614
Review-Url: https://codereview.chromium.org/2006183004
Cr-Commit-Position: refs/heads/master@{#42481}
2017-01-18 22:17:46 +00:00
|
|
|
TestData t = initial_data;
|
|
|
|
|
|
|
|
int res =
|
|
|
|
reinterpret_cast<int>(CALL_GENERATED_CODE(isolate, f, &t, 0, 0, 0, 0));
|
|
|
|
CHECK_EQ(expected_res, res);
|
|
|
|
switch (access3.size) {
|
|
|
|
case MemoryAccess::Size::Byte:
|
|
|
|
CHECK_EQ(expected_data.b, t.b);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case MemoryAccess::Size::HalfWord:
|
|
|
|
CHECK_EQ(expected_data.h, t.h);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case MemoryAccess::Size::Word:
|
|
|
|
CHECK_EQ(expected_data.w, t.w);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2017-10-18 09:46:57 +00:00
|
|
|
|
|
|
|
} // namespace
|
|
|
|
|
Implement ldrex/strex instructions in ARM simulator
This CL implements ldrex, ldrexb, ldrexh, strex, strexb, and strexh in the
Simulator. These instructions provide "exclusive" access, which provides mutual
exclusion for concurrent threads of execution.
The ARM specification gives some leeway to implementors, but essentially
describes each processor as having Local Monitor and Global Monitor. The Local
Monitor is used to check the exclusivity state without having to synchronize
with other processors. The Global Monitor is shared between processors. We
model both to make it easier to match behavior with the spec.
When running with multiple OS threads, each thread has its own isolate, and
each isolate has its own Simulator. The Local Monitor is stored directly on the
Simulator, and the Global Monitor is stored as a lazy singleton. The Global
Monitor maintains a linked-list of all Simulators.
All loads/stores (even non-exclusive) are guarded by the Global Monitor's mutex.
BUG=v8:4614
Review-Url: https://codereview.chromium.org/2006183004
Cr-Commit-Position: refs/heads/master@{#42481}
2017-01-18 22:17:46 +00:00
|
|
|
TEST(simulator_invalidate_exclusive_access) {
|
|
|
|
using Kind = MemoryAccess::Kind;
|
|
|
|
using Size = MemoryAccess::Size;
|
|
|
|
|
|
|
|
MemoryAccess ldrex_w(Kind::LoadExcl, Size::Word, offsetof(TestData, w));
|
|
|
|
MemoryAccess strex_w(Kind::StoreExcl, Size::Word, offsetof(TestData, w), 7);
|
|
|
|
|
|
|
|
// Address mismatch.
|
|
|
|
TestInvalidateExclusiveAccess(
|
|
|
|
TestData(1), ldrex_w,
|
|
|
|
MemoryAccess(Kind::LoadExcl, Size::Word, offsetof(TestData, dummy)),
|
|
|
|
strex_w, 1, TestData(1));
|
|
|
|
|
|
|
|
// Size mismatch.
|
|
|
|
TestInvalidateExclusiveAccess(
|
|
|
|
TestData(1), ldrex_w, MemoryAccess(),
|
|
|
|
MemoryAccess(Kind::StoreExcl, Size::HalfWord, offsetof(TestData, w), 7),
|
|
|
|
1, TestData(1));
|
|
|
|
|
|
|
|
// Load between ldrex/strex.
|
|
|
|
TestInvalidateExclusiveAccess(
|
|
|
|
TestData(1), ldrex_w,
|
|
|
|
MemoryAccess(Kind::Load, Size::Word, offsetof(TestData, dummy)), strex_w,
|
|
|
|
1, TestData(1));
|
|
|
|
|
|
|
|
// Store between ldrex/strex.
|
|
|
|
TestInvalidateExclusiveAccess(
|
|
|
|
TestData(1), ldrex_w,
|
|
|
|
MemoryAccess(Kind::Store, Size::Word, offsetof(TestData, dummy)), strex_w,
|
|
|
|
1, TestData(1));
|
|
|
|
|
|
|
|
// Match
|
|
|
|
TestInvalidateExclusiveAccess(TestData(1), ldrex_w, MemoryAccess(), strex_w,
|
|
|
|
0, TestData(7));
|
|
|
|
}
|
|
|
|
|
Revert "Revert "[cctest] Clarify that tests for sync instructions are simulator specific""
This reverts commit 1feadfe81b7cc250df83cbf0b2fdfd17ac348cf8.
Reason for revert: Reland as bot stayed red after revert.
Original change's description:
> Revert "[cctest] Clarify that tests for sync instructions are simulator specific"
>
> This reverts commit 4013518fe3be92f0fbd043b09017f5eb8b8629d8.
>
> Reason for revert:
> https://build.chromium.org/p/client.v8.ports/builders/V8%20Linux%20-%20arm64%20-%20sim%20-%20gc%20stress
>
> Original change's description:
> > [cctest] Clarify that tests for sync instructions are simulator specific
> >
> > Some tests were recently added to test-simulator-arm.cc, however this file is
> > meant for tests that are specific to the simulator and therefore are not written
> > to work on hardware. While this sounds surprising, the reason is that our simulation
> > of synchronisation instructions is more conservative than on hardware.
> >
> > To make this more clear, this patch renames the "test-simulator-arm{,64}.cc"
> > files to "test-sync-primitives-arm{,64}.cc", and moves the vneg and vabs tests
> > into "test-assembler-arm.cc" which is were tests that are garanteed to work in
> > either native or simulated environments live.
> >
> > Finally, take the opportunity to share a little bit of code.
> >
> > Bug: v8:6963
> > Change-Id: Ifb85d3671c823b9bba73d09f419536b089a4e87c
> > Reviewed-on: https://chromium-review.googlesource.com/749387
> > Reviewed-by: Clemens Hammacher <clemensh@chromium.org>
> > Commit-Queue: Pierre Langlois <pierre.langlois@arm.com>
> > Cr-Commit-Position: refs/heads/master@{#49073}
>
> TBR=clemensh@chromium.org,pierre.langlois@arm.com,bmeurer@chromium.org
>
> Change-Id: I1bfb4e9c7c18b716f417a84b18a14cb2e1fa3a7a
> No-Presubmit: true
> No-Tree-Checks: true
> No-Try: true
> Bug: v8:6963
> Reviewed-on: https://chromium-review.googlesource.com/750624
> Reviewed-by: Michael Achenbach <machenbach@chromium.org>
> Commit-Queue: Michael Achenbach <machenbach@chromium.org>
> Cr-Commit-Position: refs/heads/master@{#49074}
TBR=machenbach@chromium.org,clemensh@chromium.org,pierre.langlois@arm.com,bmeurer@chromium.org
Change-Id: I5af7bd3678758130534730a2f6f0b651b64c6956
No-Presubmit: true
No-Tree-Checks: true
No-Try: true
Bug: v8:6963
Reviewed-on: https://chromium-review.googlesource.com/750903
Reviewed-by: Michael Achenbach <machenbach@chromium.org>
Commit-Queue: Michael Achenbach <machenbach@chromium.org>
Cr-Commit-Position: refs/heads/master@{#49075}
2017-11-02 13:11:29 +00:00
|
|
|
namespace {
|
2017-10-19 09:14:34 +00:00
|
|
|
|
Revert "Revert "[cctest] Clarify that tests for sync instructions are simulator specific""
This reverts commit 1feadfe81b7cc250df83cbf0b2fdfd17ac348cf8.
Reason for revert: Reland as bot stayed red after revert.
Original change's description:
> Revert "[cctest] Clarify that tests for sync instructions are simulator specific"
>
> This reverts commit 4013518fe3be92f0fbd043b09017f5eb8b8629d8.
>
> Reason for revert:
> https://build.chromium.org/p/client.v8.ports/builders/V8%20Linux%20-%20arm64%20-%20sim%20-%20gc%20stress
>
> Original change's description:
> > [cctest] Clarify that tests for sync instructions are simulator specific
> >
> > Some tests were recently added to test-simulator-arm.cc, however this file is
> > meant for tests that are specific to the simulator and therefore are not written
> > to work on hardware. While this sounds surprising, the reason is that our simulation
> > of synchronisation instructions is more conservative than on hardware.
> >
> > To make this more clear, this patch renames the "test-simulator-arm{,64}.cc"
> > files to "test-sync-primitives-arm{,64}.cc", and moves the vneg and vabs tests
> > into "test-assembler-arm.cc" which is were tests that are garanteed to work in
> > either native or simulated environments live.
> >
> > Finally, take the opportunity to share a little bit of code.
> >
> > Bug: v8:6963
> > Change-Id: Ifb85d3671c823b9bba73d09f419536b089a4e87c
> > Reviewed-on: https://chromium-review.googlesource.com/749387
> > Reviewed-by: Clemens Hammacher <clemensh@chromium.org>
> > Commit-Queue: Pierre Langlois <pierre.langlois@arm.com>
> > Cr-Commit-Position: refs/heads/master@{#49073}
>
> TBR=clemensh@chromium.org,pierre.langlois@arm.com,bmeurer@chromium.org
>
> Change-Id: I1bfb4e9c7c18b716f417a84b18a14cb2e1fa3a7a
> No-Presubmit: true
> No-Tree-Checks: true
> No-Try: true
> Bug: v8:6963
> Reviewed-on: https://chromium-review.googlesource.com/750624
> Reviewed-by: Michael Achenbach <machenbach@chromium.org>
> Commit-Queue: Michael Achenbach <machenbach@chromium.org>
> Cr-Commit-Position: refs/heads/master@{#49074}
TBR=machenbach@chromium.org,clemensh@chromium.org,pierre.langlois@arm.com,bmeurer@chromium.org
Change-Id: I5af7bd3678758130534730a2f6f0b651b64c6956
No-Presubmit: true
No-Tree-Checks: true
No-Try: true
Bug: v8:6963
Reviewed-on: https://chromium-review.googlesource.com/750903
Reviewed-by: Michael Achenbach <machenbach@chromium.org>
Commit-Queue: Michael Achenbach <machenbach@chromium.org>
Cr-Commit-Position: refs/heads/master@{#49075}
2017-11-02 13:11:29 +00:00
|
|
|
int ExecuteMemoryAccess(Isolate* isolate, TestData* test_data,
|
|
|
|
MemoryAccess access) {
|
Implement ldrex/strex instructions in ARM simulator
This CL implements ldrex, ldrexb, ldrexh, strex, strexb, and strexh in the
Simulator. These instructions provide "exclusive" access, which provides mutual
exclusion for concurrent threads of execution.
The ARM specification gives some leeway to implementors, but essentially
describes each processor as having Local Monitor and Global Monitor. The Local
Monitor is used to check the exclusivity state without having to synchronize
with other processors. The Global Monitor is shared between processors. We
model both to make it easier to match behavior with the spec.
When running with multiple OS threads, each thread has its own isolate, and
each isolate has its own Simulator. The Local Monitor is stored directly on the
Simulator, and the Global Monitor is stored as a lazy singleton. The Global
Monitor maintains a linked-list of all Simulators.
All loads/stores (even non-exclusive) are guarded by the Global Monitor's mutex.
BUG=v8:4614
Review-Url: https://codereview.chromium.org/2006183004
Cr-Commit-Position: refs/heads/master@{#42481}
2017-01-18 22:17:46 +00:00
|
|
|
HandleScope scope(isolate);
|
2017-10-19 09:14:34 +00:00
|
|
|
F_piiii f = FUNCTION_CAST<F_piiii>(AssembleCode([&](Assembler& assm) {
|
2017-10-18 09:46:57 +00:00
|
|
|
AssembleMemoryAccess(&assm, access, r0, r2, r1);
|
2017-10-19 09:14:34 +00:00
|
|
|
}));
|
Implement ldrex/strex instructions in ARM simulator
This CL implements ldrex, ldrexb, ldrexh, strex, strexb, and strexh in the
Simulator. These instructions provide "exclusive" access, which provides mutual
exclusion for concurrent threads of execution.
The ARM specification gives some leeway to implementors, but essentially
describes each processor as having Local Monitor and Global Monitor. The Local
Monitor is used to check the exclusivity state without having to synchronize
with other processors. The Global Monitor is shared between processors. We
model both to make it easier to match behavior with the spec.
When running with multiple OS threads, each thread has its own isolate, and
each isolate has its own Simulator. The Local Monitor is stored directly on the
Simulator, and the Global Monitor is stored as a lazy singleton. The Global
Monitor maintains a linked-list of all Simulators.
All loads/stores (even non-exclusive) are guarded by the Global Monitor's mutex.
BUG=v8:4614
Review-Url: https://codereview.chromium.org/2006183004
Cr-Commit-Position: refs/heads/master@{#42481}
2017-01-18 22:17:46 +00:00
|
|
|
|
|
|
|
return reinterpret_cast<int>(
|
|
|
|
CALL_GENERATED_CODE(isolate, f, test_data, 0, 0, 0, 0));
|
|
|
|
}
|
|
|
|
|
Revert "Revert "[cctest] Clarify that tests for sync instructions are simulator specific""
This reverts commit 1feadfe81b7cc250df83cbf0b2fdfd17ac348cf8.
Reason for revert: Reland as bot stayed red after revert.
Original change's description:
> Revert "[cctest] Clarify that tests for sync instructions are simulator specific"
>
> This reverts commit 4013518fe3be92f0fbd043b09017f5eb8b8629d8.
>
> Reason for revert:
> https://build.chromium.org/p/client.v8.ports/builders/V8%20Linux%20-%20arm64%20-%20sim%20-%20gc%20stress
>
> Original change's description:
> > [cctest] Clarify that tests for sync instructions are simulator specific
> >
> > Some tests were recently added to test-simulator-arm.cc, however this file is
> > meant for tests that are specific to the simulator and therefore are not written
> > to work on hardware. While this sounds surprising, the reason is that our simulation
> > of synchronisation instructions is more conservative than on hardware.
> >
> > To make this more clear, this patch renames the "test-simulator-arm{,64}.cc"
> > files to "test-sync-primitives-arm{,64}.cc", and moves the vneg and vabs tests
> > into "test-assembler-arm.cc" which is were tests that are garanteed to work in
> > either native or simulated environments live.
> >
> > Finally, take the opportunity to share a little bit of code.
> >
> > Bug: v8:6963
> > Change-Id: Ifb85d3671c823b9bba73d09f419536b089a4e87c
> > Reviewed-on: https://chromium-review.googlesource.com/749387
> > Reviewed-by: Clemens Hammacher <clemensh@chromium.org>
> > Commit-Queue: Pierre Langlois <pierre.langlois@arm.com>
> > Cr-Commit-Position: refs/heads/master@{#49073}
>
> TBR=clemensh@chromium.org,pierre.langlois@arm.com,bmeurer@chromium.org
>
> Change-Id: I1bfb4e9c7c18b716f417a84b18a14cb2e1fa3a7a
> No-Presubmit: true
> No-Tree-Checks: true
> No-Try: true
> Bug: v8:6963
> Reviewed-on: https://chromium-review.googlesource.com/750624
> Reviewed-by: Michael Achenbach <machenbach@chromium.org>
> Commit-Queue: Michael Achenbach <machenbach@chromium.org>
> Cr-Commit-Position: refs/heads/master@{#49074}
TBR=machenbach@chromium.org,clemensh@chromium.org,pierre.langlois@arm.com,bmeurer@chromium.org
Change-Id: I5af7bd3678758130534730a2f6f0b651b64c6956
No-Presubmit: true
No-Tree-Checks: true
No-Try: true
Bug: v8:6963
Reviewed-on: https://chromium-review.googlesource.com/750903
Reviewed-by: Michael Achenbach <machenbach@chromium.org>
Commit-Queue: Michael Achenbach <machenbach@chromium.org>
Cr-Commit-Position: refs/heads/master@{#49075}
2017-11-02 13:11:29 +00:00
|
|
|
} // namespace
|
|
|
|
|
Implement ldrex/strex instructions in ARM simulator
This CL implements ldrex, ldrexb, ldrexh, strex, strexb, and strexh in the
Simulator. These instructions provide "exclusive" access, which provides mutual
exclusion for concurrent threads of execution.
The ARM specification gives some leeway to implementors, but essentially
describes each processor as having Local Monitor and Global Monitor. The Local
Monitor is used to check the exclusivity state without having to synchronize
with other processors. The Global Monitor is shared between processors. We
model both to make it easier to match behavior with the spec.
When running with multiple OS threads, each thread has its own isolate, and
each isolate has its own Simulator. The Local Monitor is stored directly on the
Simulator, and the Global Monitor is stored as a lazy singleton. The Global
Monitor maintains a linked-list of all Simulators.
All loads/stores (even non-exclusive) are guarded by the Global Monitor's mutex.
BUG=v8:4614
Review-Url: https://codereview.chromium.org/2006183004
Cr-Commit-Position: refs/heads/master@{#42481}
2017-01-18 22:17:46 +00:00
|
|
|
class MemoryAccessThread : public v8::base::Thread {
|
|
|
|
public:
|
|
|
|
MemoryAccessThread()
|
|
|
|
: Thread(Options("MemoryAccessThread")),
|
2017-10-13 16:33:03 +00:00
|
|
|
test_data_(nullptr),
|
Implement ldrex/strex instructions in ARM simulator
This CL implements ldrex, ldrexb, ldrexh, strex, strexb, and strexh in the
Simulator. These instructions provide "exclusive" access, which provides mutual
exclusion for concurrent threads of execution.
The ARM specification gives some leeway to implementors, but essentially
describes each processor as having Local Monitor and Global Monitor. The Local
Monitor is used to check the exclusivity state without having to synchronize
with other processors. The Global Monitor is shared between processors. We
model both to make it easier to match behavior with the spec.
When running with multiple OS threads, each thread has its own isolate, and
each isolate has its own Simulator. The Local Monitor is stored directly on the
Simulator, and the Global Monitor is stored as a lazy singleton. The Global
Monitor maintains a linked-list of all Simulators.
All loads/stores (even non-exclusive) are guarded by the Global Monitor's mutex.
BUG=v8:4614
Review-Url: https://codereview.chromium.org/2006183004
Cr-Commit-Position: refs/heads/master@{#42481}
2017-01-18 22:17:46 +00:00
|
|
|
is_finished_(false),
|
|
|
|
has_request_(false),
|
2017-10-06 11:24:42 +00:00
|
|
|
did_request_(false),
|
|
|
|
isolate_(nullptr) {}
|
Implement ldrex/strex instructions in ARM simulator
This CL implements ldrex, ldrexb, ldrexh, strex, strexb, and strexh in the
Simulator. These instructions provide "exclusive" access, which provides mutual
exclusion for concurrent threads of execution.
The ARM specification gives some leeway to implementors, but essentially
describes each processor as having Local Monitor and Global Monitor. The Local
Monitor is used to check the exclusivity state without having to synchronize
with other processors. The Global Monitor is shared between processors. We
model both to make it easier to match behavior with the spec.
When running with multiple OS threads, each thread has its own isolate, and
each isolate has its own Simulator. The Local Monitor is stored directly on the
Simulator, and the Global Monitor is stored as a lazy singleton. The Global
Monitor maintains a linked-list of all Simulators.
All loads/stores (even non-exclusive) are guarded by the Global Monitor's mutex.
BUG=v8:4614
Review-Url: https://codereview.chromium.org/2006183004
Cr-Commit-Position: refs/heads/master@{#42481}
2017-01-18 22:17:46 +00:00
|
|
|
|
|
|
|
virtual void Run() {
|
|
|
|
v8::Isolate::CreateParams create_params;
|
|
|
|
create_params.array_buffer_allocator = CcTest::array_buffer_allocator();
|
2017-10-06 11:24:42 +00:00
|
|
|
isolate_ = v8::Isolate::New(create_params);
|
|
|
|
Isolate* i_isolate = reinterpret_cast<Isolate*>(isolate_);
|
|
|
|
{
|
|
|
|
v8::Isolate::Scope scope(isolate_);
|
|
|
|
v8::base::LockGuard<v8::base::Mutex> lock_guard(&mutex_);
|
|
|
|
while (!is_finished_) {
|
|
|
|
while (!(has_request_ || is_finished_)) {
|
|
|
|
has_request_cv_.Wait(&mutex_);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (is_finished_) {
|
|
|
|
break;
|
|
|
|
}
|
Implement ldrex/strex instructions in ARM simulator
This CL implements ldrex, ldrexb, ldrexh, strex, strexb, and strexh in the
Simulator. These instructions provide "exclusive" access, which provides mutual
exclusion for concurrent threads of execution.
The ARM specification gives some leeway to implementors, but essentially
describes each processor as having Local Monitor and Global Monitor. The Local
Monitor is used to check the exclusivity state without having to synchronize
with other processors. The Global Monitor is shared between processors. We
model both to make it easier to match behavior with the spec.
When running with multiple OS threads, each thread has its own isolate, and
each isolate has its own Simulator. The Local Monitor is stored directly on the
Simulator, and the Global Monitor is stored as a lazy singleton. The Global
Monitor maintains a linked-list of all Simulators.
All loads/stores (even non-exclusive) are guarded by the Global Monitor's mutex.
BUG=v8:4614
Review-Url: https://codereview.chromium.org/2006183004
Cr-Commit-Position: refs/heads/master@{#42481}
2017-01-18 22:17:46 +00:00
|
|
|
|
2017-10-06 11:24:42 +00:00
|
|
|
ExecuteMemoryAccess(i_isolate, test_data_, access_);
|
|
|
|
has_request_ = false;
|
|
|
|
did_request_ = true;
|
|
|
|
did_request_cv_.NotifyOne();
|
Implement ldrex/strex instructions in ARM simulator
This CL implements ldrex, ldrexb, ldrexh, strex, strexb, and strexh in the
Simulator. These instructions provide "exclusive" access, which provides mutual
exclusion for concurrent threads of execution.
The ARM specification gives some leeway to implementors, but essentially
describes each processor as having Local Monitor and Global Monitor. The Local
Monitor is used to check the exclusivity state without having to synchronize
with other processors. The Global Monitor is shared between processors. We
model both to make it easier to match behavior with the spec.
When running with multiple OS threads, each thread has its own isolate, and
each isolate has its own Simulator. The Local Monitor is stored directly on the
Simulator, and the Global Monitor is stored as a lazy singleton. The Global
Monitor maintains a linked-list of all Simulators.
All loads/stores (even non-exclusive) are guarded by the Global Monitor's mutex.
BUG=v8:4614
Review-Url: https://codereview.chromium.org/2006183004
Cr-Commit-Position: refs/heads/master@{#42481}
2017-01-18 22:17:46 +00:00
|
|
|
}
|
|
|
|
}
|
2017-10-06 11:24:42 +00:00
|
|
|
isolate_->Dispose();
|
Implement ldrex/strex instructions in ARM simulator
This CL implements ldrex, ldrexb, ldrexh, strex, strexb, and strexh in the
Simulator. These instructions provide "exclusive" access, which provides mutual
exclusion for concurrent threads of execution.
The ARM specification gives some leeway to implementors, but essentially
describes each processor as having Local Monitor and Global Monitor. The Local
Monitor is used to check the exclusivity state without having to synchronize
with other processors. The Global Monitor is shared between processors. We
model both to make it easier to match behavior with the spec.
When running with multiple OS threads, each thread has its own isolate, and
each isolate has its own Simulator. The Local Monitor is stored directly on the
Simulator, and the Global Monitor is stored as a lazy singleton. The Global
Monitor maintains a linked-list of all Simulators.
All loads/stores (even non-exclusive) are guarded by the Global Monitor's mutex.
BUG=v8:4614
Review-Url: https://codereview.chromium.org/2006183004
Cr-Commit-Position: refs/heads/master@{#42481}
2017-01-18 22:17:46 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void NextAndWait(TestData* test_data, MemoryAccess access) {
|
|
|
|
DCHECK(!has_request_);
|
|
|
|
v8::base::LockGuard<v8::base::Mutex> lock_guard(&mutex_);
|
|
|
|
test_data_ = test_data;
|
|
|
|
access_ = access;
|
|
|
|
has_request_ = true;
|
|
|
|
has_request_cv_.NotifyOne();
|
|
|
|
while (!did_request_) {
|
|
|
|
did_request_cv_.Wait(&mutex_);
|
|
|
|
}
|
|
|
|
did_request_ = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
void Finish() {
|
|
|
|
v8::base::LockGuard<v8::base::Mutex> lock_guard(&mutex_);
|
|
|
|
is_finished_ = true;
|
|
|
|
has_request_cv_.NotifyOne();
|
|
|
|
}
|
|
|
|
|
|
|
|
private:
|
|
|
|
TestData* test_data_;
|
|
|
|
MemoryAccess access_;
|
|
|
|
bool is_finished_;
|
|
|
|
bool has_request_;
|
|
|
|
bool did_request_;
|
|
|
|
v8::base::Mutex mutex_;
|
|
|
|
v8::base::ConditionVariable has_request_cv_;
|
|
|
|
v8::base::ConditionVariable did_request_cv_;
|
2017-10-06 11:24:42 +00:00
|
|
|
v8::Isolate* isolate_;
|
Implement ldrex/strex instructions in ARM simulator
This CL implements ldrex, ldrexb, ldrexh, strex, strexb, and strexh in the
Simulator. These instructions provide "exclusive" access, which provides mutual
exclusion for concurrent threads of execution.
The ARM specification gives some leeway to implementors, but essentially
describes each processor as having Local Monitor and Global Monitor. The Local
Monitor is used to check the exclusivity state without having to synchronize
with other processors. The Global Monitor is shared between processors. We
model both to make it easier to match behavior with the spec.
When running with multiple OS threads, each thread has its own isolate, and
each isolate has its own Simulator. The Local Monitor is stored directly on the
Simulator, and the Global Monitor is stored as a lazy singleton. The Global
Monitor maintains a linked-list of all Simulators.
All loads/stores (even non-exclusive) are guarded by the Global Monitor's mutex.
BUG=v8:4614
Review-Url: https://codereview.chromium.org/2006183004
Cr-Commit-Position: refs/heads/master@{#42481}
2017-01-18 22:17:46 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
TEST(simulator_invalidate_exclusive_access_threaded) {
|
|
|
|
using Kind = MemoryAccess::Kind;
|
|
|
|
using Size = MemoryAccess::Size;
|
|
|
|
|
|
|
|
Isolate* isolate = CcTest::i_isolate();
|
|
|
|
HandleScope scope(isolate);
|
|
|
|
|
|
|
|
TestData test_data(1);
|
|
|
|
|
|
|
|
MemoryAccessThread thread;
|
|
|
|
thread.Start();
|
|
|
|
|
|
|
|
MemoryAccess ldrex_w(Kind::LoadExcl, Size::Word, offsetof(TestData, w));
|
|
|
|
MemoryAccess strex_w(Kind::StoreExcl, Size::Word, offsetof(TestData, w), 7);
|
|
|
|
|
|
|
|
// Exclusive store completed by another thread first.
|
|
|
|
test_data = TestData(1);
|
|
|
|
thread.NextAndWait(&test_data, MemoryAccess(Kind::LoadExcl, Size::Word,
|
|
|
|
offsetof(TestData, w)));
|
|
|
|
ExecuteMemoryAccess(isolate, &test_data, ldrex_w);
|
|
|
|
thread.NextAndWait(&test_data, MemoryAccess(Kind::StoreExcl, Size::Word,
|
|
|
|
offsetof(TestData, w), 5));
|
|
|
|
CHECK_EQ(1, ExecuteMemoryAccess(isolate, &test_data, strex_w));
|
|
|
|
CHECK_EQ(5, test_data.w);
|
|
|
|
|
|
|
|
// Exclusive store completed by another thread; different address, but masked
|
|
|
|
// to same
|
|
|
|
test_data = TestData(1);
|
|
|
|
ExecuteMemoryAccess(isolate, &test_data, ldrex_w);
|
|
|
|
thread.NextAndWait(&test_data, MemoryAccess(Kind::LoadExcl, Size::Word,
|
|
|
|
offsetof(TestData, dummy)));
|
|
|
|
thread.NextAndWait(&test_data, MemoryAccess(Kind::StoreExcl, Size::Word,
|
|
|
|
offsetof(TestData, dummy), 5));
|
|
|
|
CHECK_EQ(1, ExecuteMemoryAccess(isolate, &test_data, strex_w));
|
|
|
|
CHECK_EQ(1, test_data.w);
|
|
|
|
|
|
|
|
// Test failure when store between ldrex/strex.
|
|
|
|
test_data = TestData(1);
|
|
|
|
ExecuteMemoryAccess(isolate, &test_data, ldrex_w);
|
|
|
|
thread.NextAndWait(&test_data, MemoryAccess(Kind::Store, Size::Word,
|
|
|
|
offsetof(TestData, dummy)));
|
|
|
|
CHECK_EQ(1, ExecuteMemoryAccess(isolate, &test_data, strex_w));
|
|
|
|
CHECK_EQ(1, test_data.w);
|
|
|
|
|
|
|
|
thread.Finish();
|
|
|
|
thread.Join();
|
|
|
|
}
|
|
|
|
|
2017-11-02 11:38:43 +00:00
|
|
|
#undef __
|
2017-11-01 19:07:49 +00:00
|
|
|
|
Revert "Revert "[cctest] Clarify that tests for sync instructions are simulator specific""
This reverts commit 1feadfe81b7cc250df83cbf0b2fdfd17ac348cf8.
Reason for revert: Reland as bot stayed red after revert.
Original change's description:
> Revert "[cctest] Clarify that tests for sync instructions are simulator specific"
>
> This reverts commit 4013518fe3be92f0fbd043b09017f5eb8b8629d8.
>
> Reason for revert:
> https://build.chromium.org/p/client.v8.ports/builders/V8%20Linux%20-%20arm64%20-%20sim%20-%20gc%20stress
>
> Original change's description:
> > [cctest] Clarify that tests for sync instructions are simulator specific
> >
> > Some tests were recently added to test-simulator-arm.cc, however this file is
> > meant for tests that are specific to the simulator and therefore are not written
> > to work on hardware. While this sounds surprising, the reason is that our simulation
> > of synchronisation instructions is more conservative than on hardware.
> >
> > To make this more clear, this patch renames the "test-simulator-arm{,64}.cc"
> > files to "test-sync-primitives-arm{,64}.cc", and moves the vneg and vabs tests
> > into "test-assembler-arm.cc" which is were tests that are garanteed to work in
> > either native or simulated environments live.
> >
> > Finally, take the opportunity to share a little bit of code.
> >
> > Bug: v8:6963
> > Change-Id: Ifb85d3671c823b9bba73d09f419536b089a4e87c
> > Reviewed-on: https://chromium-review.googlesource.com/749387
> > Reviewed-by: Clemens Hammacher <clemensh@chromium.org>
> > Commit-Queue: Pierre Langlois <pierre.langlois@arm.com>
> > Cr-Commit-Position: refs/heads/master@{#49073}
>
> TBR=clemensh@chromium.org,pierre.langlois@arm.com,bmeurer@chromium.org
>
> Change-Id: I1bfb4e9c7c18b716f417a84b18a14cb2e1fa3a7a
> No-Presubmit: true
> No-Tree-Checks: true
> No-Try: true
> Bug: v8:6963
> Reviewed-on: https://chromium-review.googlesource.com/750624
> Reviewed-by: Michael Achenbach <machenbach@chromium.org>
> Commit-Queue: Michael Achenbach <machenbach@chromium.org>
> Cr-Commit-Position: refs/heads/master@{#49074}
TBR=machenbach@chromium.org,clemensh@chromium.org,pierre.langlois@arm.com,bmeurer@chromium.org
Change-Id: I5af7bd3678758130534730a2f6f0b651b64c6956
No-Presubmit: true
No-Tree-Checks: true
No-Try: true
Bug: v8:6963
Reviewed-on: https://chromium-review.googlesource.com/750903
Reviewed-by: Michael Achenbach <machenbach@chromium.org>
Commit-Queue: Michael Achenbach <machenbach@chromium.org>
Cr-Commit-Position: refs/heads/master@{#49075}
2017-11-02 13:11:29 +00:00
|
|
|
#endif // defined(USE_SIMULATOR)
|
|
|
|
|
2017-08-31 12:34:55 +00:00
|
|
|
} // namespace internal
|
|
|
|
} // namespace v8
|