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[riscv64] Optimize xori and branch in FloatMinMaxHelper

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xori rd, rs, 0x1 mean is that negating bit 0 of rs.
  So we can delte xori and invert the condition of the branch.

Change-Id: I318b7a2def6ec5d848757f85623564922abfcdc5
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2847673
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Brice Dobry <brice.dobry@futurewei.com>
Cr-Commit-Position: refs/heads/master@{#74197}
This commit is contained in:
Lu Yahan 2021-04-27 10:45:50 +08:00 committed by Commit Bot
parent 1bf7fe3a6e
commit 00016e5e3d
2 changed files with 21 additions and 9 deletions
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28
src/codegen/riscv64/macro-assembler-riscv64.cc
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@ -2058,8 +2058,8 @@ void TurboAssembler::CompareF64(Register rd, FPUCondition cc, FPURegister cmp1,
}
}
void TurboAssembler::CompareIsNanF32(Register rd, FPURegister cmp1,
FPURegister cmp2) {
void TurboAssembler::CompareIsNotNanF32(Register rd, FPURegister cmp1,
FPURegister cmp2) {
UseScratchRegisterScope temps(this);
BlockTrampolinePoolScope block_trampoline_pool(this);
Register scratch = temps.Acquire();
@ -2067,11 +2067,10 @@ void TurboAssembler::CompareIsNanF32(Register rd, FPURegister cmp1,
feq_s(rd, cmp1, cmp1); // rd <- !isNan(cmp1)
feq_s(scratch, cmp2, cmp2); // scratch <- !isNaN(cmp2)
And(rd, rd, scratch); // rd <- !isNan(cmp1) && !isNan(cmp2)
Xor(rd, rd, 1); // rd <- isNan(cmp1) || isNan(cmp2)
}
void TurboAssembler::CompareIsNanF64(Register rd, FPURegister cmp1,
FPURegister cmp2) {
void TurboAssembler::CompareIsNotNanF64(Register rd, FPURegister cmp1,
FPURegister cmp2) {
UseScratchRegisterScope temps(this);
BlockTrampolinePoolScope block_trampoline_pool(this);
Register scratch = temps.Acquire();
@ -2079,7 +2078,18 @@ void TurboAssembler::CompareIsNanF64(Register rd, FPURegister cmp1,
feq_d(rd, cmp1, cmp1); // rd <- !isNan(cmp1)
feq_d(scratch, cmp2, cmp2); // scratch <- !isNaN(cmp2)
And(rd, rd, scratch); // rd <- !isNan(cmp1) && !isNan(cmp2)
Xor(rd, rd, 1); // rd <- isNan(cmp1) || isNan(cmp2)
}
void TurboAssembler::CompareIsNanF32(Register rd, FPURegister cmp1,
FPURegister cmp2) {
CompareIsNotNanF32(rd, cmp1, cmp2); // rd <- !isNan(cmp1) && !isNan(cmp2)
Xor(rd, rd, 1); // rd <- isNan(cmp1) || isNan(cmp2)
}
void TurboAssembler::CompareIsNanF64(Register rd, FPURegister cmp1,
FPURegister cmp2) {
CompareIsNotNanF64(rd, cmp1, cmp2); // rd <- !isNan(cmp1) && !isNan(cmp2)
Xor(rd, rd, 1); // rd <- isNan(cmp1) || isNan(cmp2)
}
void TurboAssembler::BranchTrueShortF(Register rs, Label* target) {
@ -4319,11 +4329,11 @@ void TurboAssembler::FloatMinMaxHelper(FPURegister dst, FPURegister src1,
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
if (std::is_same<float, F_TYPE>::value) {
CompareIsNanF32(scratch, src1, src2);
CompareIsNotNanF32(scratch, src1, src2);
} else {
CompareIsNanF64(scratch, src1, src2);
CompareIsNotNanF64(scratch, src1, src2);
}
BranchTrueF(scratch, &nan);
BranchFalseF(scratch, &nan);
if (kind == MaxMinKind::kMax) {
if (std::is_same<float, F_TYPE>::value) {

2
src/codegen/riscv64/macro-assembler-riscv64.h
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@ -167,6 +167,8 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
// Compare double, if any operand is NaN, result is false except for NE
void CompareF64(Register rd, FPUCondition cc, FPURegister cmp1,
FPURegister cmp2);
void CompareIsNotNanF32(Register rd, FPURegister cmp1, FPURegister cmp2);
void CompareIsNotNanF64(Register rd, FPURegister cmp1, FPURegister cmp2);
void CompareIsNanF32(Register rd, FPURegister cmp1, FPURegister cmp2);
void CompareIsNanF64(Register rd, FPURegister cmp1, FPURegister cmp2);