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Remove use of register r7 because llvm now issues an

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error when "r7" is used (starting in commit d85b3877)

Bug: chromium:1073270
Change-Id: I7ec8112f170b98d2edaf92bc9341e738f8de07a3
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2163435
Reviewed-by: Nico Weber <thakis@chromium.org>
Reviewed-by: Ross McIlroy <rmcilroy@chromium.org>
Commit-Queue: Nico Weber <thakis@chromium.org>
Cr-Commit-Position: refs/heads/master@{#67371}
This commit is contained in:
Amy Huang 2020-04-23 11:25:53 -07:00 committed by Commit Bot
parent 4681371139
commit 00604cd280
1 changed files with 0 additions and 13 deletions
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13
src/codegen/arm/cpu-arm.cc
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@ -37,18 +37,6 @@ V8_NOINLINE void CpuFeatures::FlushICache(void* start, size_t size) {
register uint32_t end asm("r1") = beg + size;
register uint32_t flg asm("r2") = 0;
#ifdef __clang__
// This variant of the asm avoids a constant pool entry, which can be
// problematic when LTO'ing. It is also slightly shorter.
register uint32_t scno asm("r7") = __ARM_NR_cacheflush;
asm volatile("svc 0\n"
:
: "r"(beg), "r"(end), "r"(flg), "r"(scno)
: "memory");
#else
// Use a different variant of the asm with GCC because some versions doesn't
// support r7 as an asm input.
asm volatile(
// This assembly works for both ARM and Thumb targets.
@ -66,7 +54,6 @@ V8_NOINLINE void CpuFeatures::FlushICache(void* start, size_t size) {
: "r"(beg), "r"(end), "r"(flg), [scno] "i"(__ARM_NR_cacheflush)
: "memory");
#endif
#endif
#endif // !USE_SIMULATOR
}