[maglev] Fix unbalanced push in deferred write barrier
We check page flags in the deferred write barrier, and bail out early if pointers to that page are not interesting. Make sure that the slot register saving happens after that early bailout, to avoid unbalanced push/pop. To avoid bugs like this in the future, add a stack size check as a prefix to every node's code gen. Bug: v8:7700 Change-Id: I54a00fcbc843d473a1ca1e6cf3d852a0c60621c0 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3769695 Reviewed-by: Igor Sheludko <ishell@chromium.org> Auto-Submit: Leszek Swirski <leszeks@chromium.org> Commit-Queue: Igor Sheludko <ishell@chromium.org> Cr-Commit-Position: refs/heads/main@{#81780}
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@ -131,6 +131,15 @@ class MaglevCodeGeneratingNodeProcessor {
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__ RecordComment(ss.str());
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}
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if (FLAG_debug_code) {
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__ movq(kScratchRegister, rbp);
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__ subq(kScratchRegister, rsp);
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__ cmpq(kScratchRegister,
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Immediate(code_gen_state_->stack_slots() * kSystemPointerSize +
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StandardFrameConstants::kFixedFrameSizeFromFp));
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__ Assert(equal, AbortReason::kStackAccessBelowStackPointer);
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}
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// Emit Phi moves before visiting the control node.
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if (std::is_base_of<UnconditionalControlNode, NodeT>::value) {
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EmitBlockEndGapMoves(node->template Cast<UnconditionalControlNode>(),
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@ -1001,16 +1001,17 @@ void StoreTaggedFieldWithWriteBarrier::GenerateCode(
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StoreTaggedFieldWithWriteBarrier* node) {
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ASM_CODE_COMMENT_STRING(code_gen_state->masm(),
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"Write barrier slow path");
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__ CheckPageFlag(value, kScratchRegister,
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MemoryChunk::kPointersToHereAreInterestingMask, zero,
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return_label);
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Register slot_reg = WriteBarrierDescriptor::SlotAddressRegister();
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RegList saved;
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if (node->register_snapshot().live_registers.has(slot_reg)) {
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saved.set(slot_reg);
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}
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__ PushAll(saved);
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__ CheckPageFlag(value, kScratchRegister,
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MemoryChunk::kPointersToHereAreInterestingMask, zero,
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return_label);
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__ PushAll(saved);
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__ leaq(slot_reg, FieldOperand(object, node->offset()));
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SaveFPRegsMode const save_fp_mode =
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