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[mips][wasm-simd] Implement f64x2 abs neg for mips

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Port afbbfcbe1c

R=xwafish@gmail.com

Change-Id: Iab3a9f32d8bccddcdca8d9a874869e62ae961948
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1868558
Auto-Submit: Mu Tao <pamilty@gmail.com>
Reviewed-by: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Jakob Gruber <jgruber@chromium.org>
Commit-Queue: Jakob Gruber <jgruber@chromium.org>
Cr-Commit-Position: refs/heads/master@{#64491}
This commit is contained in:
Mu Tao 2019-10-19 16:59:27 +08:00 committed by Commit Bot
parent da0ef75fde
commit 04368bbbf8
8 changed files with 33 additions and 1 deletions
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10
src/compiler/backend/mips/code-generator-mips.cc
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@ -1942,6 +1942,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(1));
break;
}
case kMipsF64x2Abs: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ bclri_d(i.OutputSimd128Register(), i.InputSimd128Register(0), 63);
break;
}
case kMipsF64x2Neg: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ bnegi_d(i.OutputSimd128Register(), i.InputSimd128Register(0), 63);
break;
}
case kMipsF32x4Splat: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ FmoveLow(kScratchReg, i.InputSingleRegister(0));

2
src/compiler/backend/mips/instruction-codes-mips.h
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@ -142,6 +142,8 @@ namespace compiler {
V(MipsI32x4Add) \
V(MipsI32x4AddHoriz) \
V(MipsI32x4Sub) \
V(MipsF64x2Abs) \
V(MipsF64x2Neg) \
V(MipsF32x4Splat) \
V(MipsF32x4ExtractLane) \
V(MipsF32x4ReplaceLane) \

2
src/compiler/backend/mips/instruction-scheduler-mips.cc
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@ -41,6 +41,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMipsDivS:
case kMipsDivU:
case kMipsExt:
case kMipsF64x2Abs:
case kMipsF64x2Neg:
case kMipsF32x4Abs:
case kMipsF32x4Add:
case kMipsF32x4AddHoriz:

2
src/compiler/backend/mips/instruction-selector-mips.cc
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@ -2014,6 +2014,8 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I8x16)
#define SIMD_UNOP_LIST(V) \
V(F64x2Abs, kMipsF64x2Abs) \
V(F64x2Neg, kMipsF64x2Neg) \
V(F32x4SConvertI32x4, kMipsF32x4SConvertI32x4) \
V(F32x4UConvertI32x4, kMipsF32x4UConvertI32x4) \
V(F32x4Abs, kMipsF32x4Abs) \

10
src/compiler/backend/mips64/code-generator-mips64.cc
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@ -2057,6 +2057,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(1));
break;
}
case kMips64F64x2Abs: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ bclri_d(i.OutputSimd128Register(), i.InputSimd128Register(0), 63);
break;
}
case kMips64F64x2Neg: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ bnegi_d(i.OutputSimd128Register(), i.InputSimd128Register(0), 63);
break;
}
case kMips64F32x4Splat: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ FmoveLow(kScratchReg, i.InputSingleRegister(0));

2
src/compiler/backend/mips64/instruction-codes-mips64.h
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@ -172,6 +172,8 @@ namespace compiler {
V(Mips64I32x4Add) \
V(Mips64I32x4AddHoriz) \
V(Mips64I32x4Sub) \
V(Mips64F64x2Abs) \
V(Mips64F64x2Neg) \
V(Mips64F32x4Splat) \
V(Mips64F32x4ExtractLane) \
V(Mips64F32x4ReplaceLane) \

2
src/compiler/backend/mips64/instruction-scheduler-mips64.cc
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@ -69,6 +69,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMips64Dsub:
case kMips64DsubOvf:
case kMips64Ext:
case kMips64F64x2Abs:
case kMips64F64x2Neg:
case kMips64F32x4Abs:
case kMips64F32x4Add:
case kMips64F32x4AddHoriz:

2
src/compiler/backend/mips64/instruction-selector-mips64.cc
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@ -2677,6 +2677,8 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I8x16)
#define SIMD_UNOP_LIST(V) \
V(F64x2Abs, kMips64F64x2Abs) \
V(F64x2Neg, kMips64F64x2Neg) \
V(F32x4SConvertI32x4, kMips64F32x4SConvertI32x4) \
V(F32x4UConvertI32x4, kMips64F32x4UConvertI32x4) \
V(F32x4Abs, kMips64F32x4Abs) \