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Fix assembler and disassembler for vblendvpd

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blendvpd should not be defined in the macro list, since the AVX version
has 4 operands, not 3.

Change-Id: Id020b460fa1a3510a91490f3b2286024cc6c5994
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1990139
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Cr-Commit-Position: refs/heads/master@{#65771}
This commit is contained in:
Ng Zhi An 2020-01-10 09:54:44 -08:00 committed by Commit Bot
parent ec25352fb7
commit 06fa66fec6
4 changed files with 25 additions and 1 deletions
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8
src/codegen/x64/assembler-x64.h
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@ -960,6 +960,7 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
SSE4_INSTRUCTION_LIST(DECLARE_SSE4_INSTRUCTION)
SSE4_PMOV_INSTRUCTION_LIST(DECLARE_SSE4_INSTRUCTION)
DECLARE_SSE4_INSTRUCTION(blendvpd, 66, 0F, 38, 15)
#undef DECLARE_SSE4_INSTRUCTION
#define DECLARE_SSE4_EXTRACT_INSTRUCTION(instruction, prefix, escape1, \
@ -1007,6 +1008,13 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
SSE4_2_INSTRUCTION_LIST(DECLARE_SSE34_AVX_INSTRUCTION)
#undef DECLARE_SSE34_AVX_INSTRUCTION
void vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2,
XMMRegister mask) {
vinstr(0x4B, dst, src1, src2, k66, k0F3A, kW0);
// The mask operand is encoded in bits[7:4] of the immediate byte.
emit(mask.code() << 4);
}
#define DECLARE_SSE4_PMOV_AVX_INSTRUCTION(instruction, prefix, escape1, \
escape2, opcode) \
void v##instruction(XMMRegister dst, XMMRegister src) { \

1
src/codegen/x64/sse-instr.h
View File

@ -132,7 +132,6 @@
V(psignd, 66, 0F, 38, 0A)
#define SSE4_INSTRUCTION_LIST(V) \
V(blendvpd, 66, 0F, 38, 15) \
V(pcmpeqq, 66, 0F, 38, 29) \
V(ptest, 66, 0F, 38, 17) \
V(packusdw, 66, 0F, 38, 2B) \

13
src/diagnostics/x64/disasm-x64.cc
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@ -998,6 +998,13 @@ int DisassemblerX64::AVXInstruction(byte* data) {
current += PrintRightOperand(current);
AppendToBuffer(",0x%x", *current++);
break;
case 0x4B: {
AppendToBuffer("vblendvpd %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
AppendToBuffer(",%s", NameOfXMMRegister((*current++) >> 4));
break;
}
default:
UnimplementedInstruction();
}
@ -1784,6 +1791,12 @@ int DisassemblerX64::TwoByteOpcodeInstruction(byte* data) {
current = data + 3;
get_modrm(*current, &mod, &regop, &rm);
switch (third_byte) {
case 0x15: {
AppendToBuffer("blendvpd %s,", NameOfXMMRegister(regop));
current += PrintRightXMMOperand(current);
AppendToBuffer(",<xmm0>");
break;
}
#define SSE34_DIS_CASE(instruction, notUsed1, notUsed2, notUsed3, opcode) \
case 0x##opcode: { \
AppendToBuffer(#instruction " %s,", NameOfXMMRegister(regop)); \

4
test/cctest/test-disasm-x64.cc
View File

@ -565,6 +565,8 @@ TEST(DisasmX64) {
__ cvtps2dq(xmm5, Operand(rdx, 4));
__ cvtdq2ps(xmm5, xmm1);
__ cvtdq2ps(xmm5, Operand(rdx, 4));
__ blendvpd(xmm5, xmm1);
__ blendvpd(xmm5, Operand(rdx, 4));
SSE4_INSTRUCTION_LIST(EMIT_SSE34_INSTR)
SSE4_PMOV_INSTRUCTION_LIST(EMIT_SSE34_INSTR)
@ -785,6 +787,8 @@ TEST(DisasmX64) {
__ vpblendw(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 23);
__ vpalignr(xmm1, xmm2, xmm3, 4);
__ vblendvpd(xmm1, xmm2, xmm3, xmm4);
__ vmovddup(xmm1, xmm2);
__ vmovddup(xmm1, Operand(rbx, rcx, times_4, 10000));
__ vbroadcastss(xmm1, Operand(rbx, rcx, times_4, 10000));