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PPC[liftoff]: Implement simd integer to fp extension

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Change-Id: I64520cd3a93821ad51f846cb2ed5475a49015734
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3996805
Reviewed-by: Junliang Yan <junyan@redhat.com>
Commit-Queue: Milad Farazmand <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/main@{#84001}
This commit is contained in:
Milad Fa 2022-11-01 11:28:08 -04:00 committed by V8 LUCI CQ
parent c2c2ef3775
commit 08c5a39495
4 changed files with 33 additions and 24 deletions
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20
src/codegen/ppc/macro-assembler-ppc.cc
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@ -4268,6 +4268,26 @@ void TurboAssembler::I8x16UConvertI16x8(Simd128Register dst,
vpkshus(dst, src2, src1);
}
void TurboAssembler::F64x2ConvertLowI32x4S(Simd128Register dst,
Simd128Register src) {
vupklsw(dst, src);
xvcvsxddp(dst, dst);
}
void TurboAssembler::F64x2ConvertLowI32x4U(Simd128Register dst,
Simd128Register src,
Register scratch1,
Simd128Register scratch2) {
constexpr int lane_width_in_bytes = 8;
vupklsw(dst, src);
// Zero extend.
mov(scratch1, Operand(0xFFFFFFFF));
mtvsrd(scratch2, scratch1);
vinsertd(scratch2, scratch2, Operand(1 * lane_width_in_bytes));
vand(dst, scratch2, dst);
xvcvuxddp(dst, dst);
}
void TurboAssembler::I64x2UConvertI32x4Low(Simd128Register dst,
Simd128Register src,
Register scratch1,

3
src/codegen/ppc/macro-assembler-ppc.h
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@ -1216,6 +1216,7 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
V(F32x4Floor) \
V(F32x4Trunc) \
V(I64x2Neg) \
V(F64x2ConvertLowI32x4S) \
V(I64x2SConvertI32x4Low) \
V(I64x2SConvertI32x4High) \
V(I32x4Neg) \
@ -1305,6 +1306,8 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
Simd128Register scratch1, Simd128Register scratch2);
void F64x2Max(Simd128Register dst, Simd128Register src1, Simd128Register src2,
Simd128Register scratch1, Simd128Register scratch2);
void F64x2ConvertLowI32x4U(Simd128Register dst, Simd128Register src,
Register scratch1, Simd128Register scratch2);
void I64x2UConvertI32x4Low(Simd128Register dst, Simd128Register src,
Register scratch1, Simd128Register scratch2);
void I64x2UConvertI32x4High(Simd128Register dst, Simd128Register src,

25
src/compiler/backend/ppc/code-generator-ppc.cc
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@ -2347,6 +2347,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
V(F32x4Ceil) \
V(F32x4Floor) \
V(F32x4Trunc) \
V(F64x2ConvertLowI32x4S) \
V(I64x2SConvertI32x4Low) \
V(I64x2SConvertI32x4High) \
V(I32x4SConvertI16x8Low) \
@ -2599,6 +2600,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ xvcvuxwsp(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kPPC_F64x2ConvertLowI32x4U: {
__ F64x2ConvertLowI32x4U(i.OutputSimd128Register(),
i.InputSimd128Register(0), kScratchReg,
kScratchSimd128Reg);
break;
}
case kPPC_I64x2UConvertI32x4Low: {
__ I64x2UConvertI32x4Low(i.OutputSimd128Register(),
i.InputSimd128Register(0), kScratchReg,
@ -3105,24 +3112,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
#undef EXT_MUL
case kPPC_F64x2ConvertLowI32x4S: {
__ vupklsw(kScratchSimd128Reg, i.InputSimd128Register(0));
__ xvcvsxddp(i.OutputSimd128Register(), kScratchSimd128Reg);
break;
}
case kPPC_F64x2ConvertLowI32x4U: {
Simd128Register dst = i.OutputSimd128Register();
constexpr int lane_width_in_bytes = 8;
__ vupklsw(dst, i.InputSimd128Register(0));
// Zero extend.
__ mov(ip, Operand(0xFFFFFFFF));
__ mtvsrd(kScratchSimd128Reg, ip);
__ vinsertd(kScratchSimd128Reg, kScratchSimd128Reg,
Operand(1 * lane_width_in_bytes));
__ vand(dst, kScratchSimd128Reg, dst);
__ xvcvuxddp(dst, dst);
break;
}
case kPPC_F64x2PromoteLowF32x4: {
constexpr int lane_number = 8;
Simd128Register src = i.InputSimd128Register(0);

9
src/wasm/baseline/ppc/liftoff-assembler-ppc.h
View File

@ -1951,6 +1951,7 @@ SIMD_SHIFT_RI_LIST(EMIT_SIMD_SHIFT_RI)
V(f32x4_floor, F32x4Floor, true, bool) \
V(f32x4_trunc, F32x4Trunc, true, bool) \
V(i64x2_neg, I64x2Neg, , void) \
V(f64x2_convert_low_i32x4_s, F64x2ConvertLowI32x4S, , void) \
V(i64x2_sconvert_i32x4_low, I64x2SConvertI32x4Low, , void) \
V(i64x2_sconvert_i32x4_high, I64x2SConvertI32x4High, , void) \
V(i32x4_neg, I32x4Neg, , void) \
@ -2236,14 +2237,10 @@ void LiftoffAssembler::emit_f64x2_relaxed_max(LiftoffRegister dst,
bailout(kRelaxedSimd, "emit_f64x2_relaxed_max");
}
void LiftoffAssembler::emit_f64x2_convert_low_i32x4_s(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "f64x2.convert_low_i32x4_s");
}
void LiftoffAssembler::emit_f64x2_convert_low_i32x4_u(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "f64x2.convert_low_i32x4_u");
F64x2ConvertLowI32x4U(dst.fp().toSimd(), src.fp().toSimd(), r0,
kScratchSimd128Reg);
}
void LiftoffAssembler::emit_f64x2_promote_low_f32x4(LiftoffRegister dst,