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[wasm-simd][liftoff][arm][arm64] Implement v128.load_zero

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Implement v128.load32_zero and v128.load64_zero on Liftoff, for ARM and
ARM64.

Bug: v8:11038
Change-Id: I5f845aca23f10b1a45a7ce9d1eb5bea0c1a22a55
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2486237
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Clemens Backes <clemensb@chromium.org>
Cr-Commit-Position: refs/heads/master@{#70784}
This commit is contained in:
Zhi An Ng 2020-10-27 06:32:58 +00:00 committed by Commit Bot
parent 2e2dc986e9
commit 095d98addf
2 changed files with 17 additions and 2 deletions
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12
src/wasm/baseline/arm/liftoff-assembler-arm.h
View File

@ -2258,7 +2258,17 @@ void LiftoffAssembler::LoadTransform(LiftoffRegister dst, Register src_addr,
vmovl(NeonU32, liftoff::GetSimd128Register(dst), dst.low_fp());
}
} else if (transform == LoadTransformationKind::kZeroExtend) {
bailout(kSimd, "v128.load_zero unimplemented");
Simd128Register dest = liftoff::GetSimd128Register(dst);
if (memtype == MachineType::Int32()) {
vmov(dest, 0);
vld1s(Neon32, NeonListOperand(dst.low_fp()), 0,
NeonMemOperand(actual_src_addr));
} else {
DCHECK_EQ(MachineType::Int64(), memtype);
vmov(dest.high(), 0);
vld1(Neon64, NeonListOperand(dest.low()),
NeonMemOperand(actual_src_addr));
}
} else {
DCHECK_EQ(LoadTransformationKind::kSplat, transform);
if (memtype == MachineType::Int8()) {

7
src/wasm/baseline/arm64/liftoff-assembler-arm64.h
View File

@ -1506,7 +1506,12 @@ void LiftoffAssembler::LoadTransform(LiftoffRegister dst, Register src_addr,
Uxtl(dst.fp().V2D(), dst.fp().V2S());
}
} else if (transform == LoadTransformationKind::kZeroExtend) {
bailout(kSimd, "v128.load_zero unimplemented");
if (memtype == MachineType::Int32()) {
Ldr(dst.fp().S(), src_op);
} else {
DCHECK_EQ(MachineType::Int64(), memtype);
Ldr(dst.fp().D(), src_op);
}
} else {
// ld1r only allows no offset or post-index, so emit an add.
DCHECK_EQ(LoadTransformationKind::kSplat, transform);