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[loong64][mips64] Cleanup some macros

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Besides, fix a error in GetMemOp.

Port commit 247b33e921

Change-Id: I34cf0d22870f438fb6bfcd67ef50ec254fb92608
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3869758
Auto-Submit: Liu Yu <liuyu@loongson.cn>
Reviewed-by: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Commit-Queue: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Cr-Commit-Position: refs/heads/main@{#82928}
This commit is contained in:
Liu Yu 2022-09-02 14:43:20 +08:00 committed by V8 LUCI CQ
parent 2b5f239abe
commit 09aded5467
4 changed files with 468 additions and 413 deletions
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9
src/compiler/backend/loong64/instruction-codes-loong64.h
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@ -186,6 +186,8 @@ namespace compiler {
V(Loong64F64x2ConvertLowI32x4S) \
V(Loong64F64x2ConvertLowI32x4U) \
V(Loong64F64x2PromoteLowF32x4) \
V(Loong64F64x2RelaxedMin) \
V(Loong64F64x2RelaxedMax) \
V(Loong64I64x2Splat) \
V(Loong64I64x2ExtractLane) \
V(Loong64I64x2ReplaceLane) \
@ -229,6 +231,8 @@ namespace compiler {
V(Loong64F32x4Trunc) \
V(Loong64F32x4NearestInt) \
V(Loong64F32x4DemoteF64x2Zero) \
V(Loong64F32x4RelaxedMin) \
V(Loong64F32x4RelaxedMax) \
V(Loong64I32x4SConvertF32x4) \
V(Loong64I32x4UConvertF32x4) \
V(Loong64I32x4Neg) \
@ -241,6 +245,10 @@ namespace compiler {
V(Loong64I32x4DotI16x8S) \
V(Loong64I32x4TruncSatF64x2SZero) \
V(Loong64I32x4TruncSatF64x2UZero) \
V(Loong64I32x4RelaxedTruncF32x4S) \
V(Loong64I32x4RelaxedTruncF32x4U) \
V(Loong64I32x4RelaxedTruncF64x2SZero) \
V(Loong64I32x4RelaxedTruncF64x2UZero) \
V(Loong64I16x8Splat) \
V(Loong64I16x8ExtractLaneU) \
V(Loong64I16x8ExtractLaneS) \
@ -270,6 +278,7 @@ namespace compiler {
V(Loong64I16x8Abs) \
V(Loong64I16x8BitMask) \
V(Loong64I16x8Q15MulRSatS) \
V(Loong64I16x8RelaxedQ15MulRS) \
V(Loong64I8x16Splat) \
V(Loong64I8x16ExtractLaneU) \
V(Loong64I8x16ExtractLaneS) \

25
src/compiler/backend/loong64/instruction-selector-loong64.cc
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@ -2724,6 +2724,10 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I32x4BitMask, kLoong64I32x4BitMask) \
V(I32x4TruncSatF64x2SZero, kLoong64I32x4TruncSatF64x2SZero) \
V(I32x4TruncSatF64x2UZero, kLoong64I32x4TruncSatF64x2UZero) \
V(I32x4RelaxedTruncF32x4S, kLoong64I32x4RelaxedTruncF32x4S) \
V(I32x4RelaxedTruncF32x4U, kLoong64I32x4RelaxedTruncF32x4U) \
V(I32x4RelaxedTruncF64x2SZero, kLoong64I32x4RelaxedTruncF64x2SZero) \
V(I32x4RelaxedTruncF64x2UZero, kLoong64I32x4RelaxedTruncF64x2UZero) \
V(I16x8Neg, kLoong64I16x8Neg) \
V(I16x8SConvertI8x16Low, kLoong64I16x8SConvertI8x16Low) \
V(I16x8SConvertI8x16High, kLoong64I16x8SConvertI8x16High) \
@ -2767,6 +2771,8 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(F64x2Ne, kLoong64F64x2Ne) \
V(F64x2Lt, kLoong64F64x2Lt) \
V(F64x2Le, kLoong64F64x2Le) \
V(F64x2RelaxedMin, kLoong64F64x2RelaxedMin) \
V(F64x2RelaxedMax, kLoong64F64x2RelaxedMax) \
V(I64x2Eq, kLoong64I64x2Eq) \
V(I64x2Ne, kLoong64I64x2Ne) \
V(I64x2Add, kLoong64I64x2Add) \
@ -2784,6 +2790,8 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(F32x4Ne, kLoong64F32x4Ne) \
V(F32x4Lt, kLoong64F32x4Lt) \
V(F32x4Le, kLoong64F32x4Le) \
V(F32x4RelaxedMin, kLoong64F32x4RelaxedMin) \
V(F32x4RelaxedMax, kLoong64F32x4RelaxedMax) \
V(I32x4Add, kLoong64I32x4Add) \
V(I32x4Sub, kLoong64I32x4Sub) \
V(I32x4Mul, kLoong64I32x4Mul) \
@ -2819,6 +2827,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I16x8SConvertI32x4, kLoong64I16x8SConvertI32x4) \
V(I16x8UConvertI32x4, kLoong64I16x8UConvertI32x4) \
V(I16x8Q15MulRSatS, kLoong64I16x8Q15MulRSatS) \
V(I16x8RelaxedQ15MulRS, kLoong64I16x8RelaxedQ15MulRS) \
V(I8x16Add, kLoong64I8x16Add) \
V(I8x16AddSatS, kLoong64I8x16AddSatS) \
V(I8x16AddSatU, kLoong64I8x16AddSatU) \
@ -2921,6 +2930,22 @@ void InstructionSelector::VisitS128Select(Node* node) {
VisitRRRR(this, kLoong64S128Select, node);
}
void InstructionSelector::VisitI8x16RelaxedLaneSelect(Node* node) {
VisitS128Select(node);
}
void InstructionSelector::VisitI16x8RelaxedLaneSelect(Node* node) {
VisitS128Select(node);
}
void InstructionSelector::VisitI32x4RelaxedLaneSelect(Node* node) {
VisitS128Select(node);
}
void InstructionSelector::VisitI64x2RelaxedLaneSelect(Node* node) {
VisitS128Select(node);
}
#if V8_ENABLE_WEBASSEMBLY
namespace {

21
src/compiler/backend/mips64/instruction-selector-mips64.cc
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@ -3161,6 +3161,26 @@ SIMD_SHIFT_OP_LIST(SIMD_VISIT_SHIFT_OP)
SIMD_BINOP_LIST(SIMD_VISIT_BINOP)
#undef SIMD_VISIT_BINOP
#define SIMD_RELAXED_OP_LIST(V) \
V(F64x2RelaxedMin) \
V(F64x2RelaxedMax) \
V(F32x4RelaxedMin) \
V(F32x4RelaxedMax) \
V(I32x4RelaxedTruncF32x4S) \
V(I32x4RelaxedTruncF32x4U) \
V(I32x4RelaxedTruncF64x2SZero) \
V(I32x4RelaxedTruncF64x2UZero) \
V(I16x8RelaxedQ15MulRS) \
V(I8x16RelaxedLaneSelect) \
V(I16x8RelaxedLaneSelect) \
V(I32x4RelaxedLaneSelect) \
V(I64x2RelaxedLaneSelect)
#define SIMD_VISIT_RELAXED_OP(Name) \
void InstructionSelector::Visit##Name(Node* node) { UNREACHABLE(); }
SIMD_RELAXED_OP_LIST(SIMD_VISIT_RELAXED_OP)
#undef SIMD_VISIT_SHIFT_OP
void InstructionSelector::VisitS128Select(Node* node) {
VisitRRRR(this, kMips64S128Select, node);
}
@ -3409,6 +3429,7 @@ InstructionSelector::AlignmentRequirements() {
#undef SIMD_BINOP_LIST
#undef SIMD_SHIFT_OP_LIST
#undef SIMD_RELAXED_OP_LIST
#undef SIMD_UNOP_LIST
#undef SIMD_TYPE_LIST
#undef TRACE_UNIMPL

2
src/wasm/baseline/mips64/liftoff-assembler-mips64.h
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@ -83,7 +83,7 @@ inline MemOperand GetMemOp(LiftoffAssembler* assm, Register addr,
bool i64_offset = false, unsigned shift_amount = 0) {
if (offset != no_reg) {
if (!i64_offset) {
assm->Dext(kScratchReg2, offset, 0, 32);
assm->Dext(kScratchReg, offset, 0, 32);
offset = kScratchReg;
}
if (shift_amount != 0) {