Move definitions of named registers as constant structures to assembler-arm.h file.
Review URL: http://codereview.chromium.org/660256 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3983 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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whesse@chromium.org
parent
dee0b9d636
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09e3bac689
@ -80,100 +80,6 @@ void CpuFeatures::Probe() {
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}
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// -----------------------------------------------------------------------------
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// Implementation of Register and CRegister
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Register no_reg = { -1 };
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Register r0 = { 0 };
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Register r1 = { 1 };
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Register r2 = { 2 };
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Register r3 = { 3 };
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Register r4 = { 4 };
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Register r5 = { 5 };
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Register r6 = { 6 };
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Register r7 = { 7 };
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Register r8 = { 8 }; // Used as context register.
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Register r9 = { 9 };
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Register r10 = { 10 }; // Used as roots register.
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Register fp = { 11 };
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Register ip = { 12 };
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Register sp = { 13 };
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Register lr = { 14 };
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Register pc = { 15 };
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CRegister no_creg = { -1 };
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CRegister cr0 = { 0 };
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CRegister cr1 = { 1 };
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CRegister cr2 = { 2 };
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CRegister cr3 = { 3 };
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CRegister cr4 = { 4 };
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CRegister cr5 = { 5 };
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CRegister cr6 = { 6 };
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CRegister cr7 = { 7 };
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CRegister cr8 = { 8 };
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CRegister cr9 = { 9 };
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CRegister cr10 = { 10 };
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CRegister cr11 = { 11 };
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CRegister cr12 = { 12 };
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CRegister cr13 = { 13 };
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CRegister cr14 = { 14 };
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CRegister cr15 = { 15 };
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// Support for the VFP registers s0 to s31 (d0 to d15).
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// Note that "sN:sM" is the same as "dN/2".
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SwVfpRegister s0 = { 0 };
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SwVfpRegister s1 = { 1 };
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SwVfpRegister s2 = { 2 };
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SwVfpRegister s3 = { 3 };
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SwVfpRegister s4 = { 4 };
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SwVfpRegister s5 = { 5 };
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SwVfpRegister s6 = { 6 };
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SwVfpRegister s7 = { 7 };
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SwVfpRegister s8 = { 8 };
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SwVfpRegister s9 = { 9 };
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SwVfpRegister s10 = { 10 };
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SwVfpRegister s11 = { 11 };
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SwVfpRegister s12 = { 12 };
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SwVfpRegister s13 = { 13 };
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SwVfpRegister s14 = { 14 };
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SwVfpRegister s15 = { 15 };
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SwVfpRegister s16 = { 16 };
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SwVfpRegister s17 = { 17 };
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SwVfpRegister s18 = { 18 };
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SwVfpRegister s19 = { 19 };
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SwVfpRegister s20 = { 20 };
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SwVfpRegister s21 = { 21 };
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SwVfpRegister s22 = { 22 };
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SwVfpRegister s23 = { 23 };
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SwVfpRegister s24 = { 24 };
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SwVfpRegister s25 = { 25 };
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SwVfpRegister s26 = { 26 };
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SwVfpRegister s27 = { 27 };
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SwVfpRegister s28 = { 28 };
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SwVfpRegister s29 = { 29 };
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SwVfpRegister s30 = { 30 };
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SwVfpRegister s31 = { 31 };
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DwVfpRegister d0 = { 0 };
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DwVfpRegister d1 = { 1 };
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DwVfpRegister d2 = { 2 };
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DwVfpRegister d3 = { 3 };
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DwVfpRegister d4 = { 4 };
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DwVfpRegister d5 = { 5 };
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DwVfpRegister d6 = { 6 };
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DwVfpRegister d7 = { 7 };
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DwVfpRegister d8 = { 8 };
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DwVfpRegister d9 = { 9 };
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DwVfpRegister d10 = { 10 };
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DwVfpRegister d11 = { 11 };
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DwVfpRegister d12 = { 12 };
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DwVfpRegister d13 = { 13 };
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DwVfpRegister d14 = { 14 };
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DwVfpRegister d15 = { 15 };
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// -----------------------------------------------------------------------------
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// Implementation of RelocInfo
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@ -84,25 +84,24 @@ struct Register {
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int code_;
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};
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const Register no_reg = { -1 };
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extern Register no_reg;
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extern Register r0;
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extern Register r1;
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extern Register r2;
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extern Register r3;
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extern Register r4;
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extern Register r5;
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extern Register r6;
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extern Register r7;
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extern Register r8;
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extern Register r9;
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extern Register r10;
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extern Register fp;
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extern Register ip;
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extern Register sp;
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extern Register lr;
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extern Register pc;
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const Register r0 = { 0 };
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const Register r1 = { 1 };
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const Register r2 = { 2 };
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const Register r3 = { 3 };
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const Register r4 = { 4 };
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const Register r5 = { 5 };
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const Register r6 = { 6 };
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const Register r7 = { 7 };
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const Register r8 = { 8 }; // Used as context register.
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const Register r9 = { 9 };
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const Register r10 = { 10 }; // Used as roots register.
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const Register fp = { 11 };
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const Register ip = { 12 };
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const Register sp = { 13 };
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const Register lr = { 14 };
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const Register pc = { 15 };
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// Single word VFP register.
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struct SwVfpRegister {
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@ -139,57 +138,57 @@ struct DwVfpRegister {
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};
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// Support for VFP registers s0 to s31 (d0 to d15).
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// Support for the VFP registers s0 to s31 (d0 to d15).
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// Note that "s(N):s(N+1)" is the same as "d(N/2)".
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extern SwVfpRegister s0;
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extern SwVfpRegister s1;
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extern SwVfpRegister s2;
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extern SwVfpRegister s3;
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extern SwVfpRegister s4;
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extern SwVfpRegister s5;
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extern SwVfpRegister s6;
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extern SwVfpRegister s7;
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extern SwVfpRegister s8;
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extern SwVfpRegister s9;
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extern SwVfpRegister s10;
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extern SwVfpRegister s11;
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extern SwVfpRegister s12;
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extern SwVfpRegister s13;
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extern SwVfpRegister s14;
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extern SwVfpRegister s15;
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extern SwVfpRegister s16;
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extern SwVfpRegister s17;
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extern SwVfpRegister s18;
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extern SwVfpRegister s19;
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extern SwVfpRegister s20;
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extern SwVfpRegister s21;
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extern SwVfpRegister s22;
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extern SwVfpRegister s23;
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extern SwVfpRegister s24;
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extern SwVfpRegister s25;
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extern SwVfpRegister s26;
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extern SwVfpRegister s27;
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extern SwVfpRegister s28;
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extern SwVfpRegister s29;
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extern SwVfpRegister s30;
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extern SwVfpRegister s31;
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const SwVfpRegister s0 = { 0 };
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const SwVfpRegister s1 = { 1 };
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const SwVfpRegister s2 = { 2 };
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const SwVfpRegister s3 = { 3 };
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const SwVfpRegister s4 = { 4 };
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const SwVfpRegister s5 = { 5 };
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const SwVfpRegister s6 = { 6 };
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const SwVfpRegister s7 = { 7 };
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const SwVfpRegister s8 = { 8 };
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const SwVfpRegister s9 = { 9 };
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const SwVfpRegister s10 = { 10 };
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const SwVfpRegister s11 = { 11 };
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const SwVfpRegister s12 = { 12 };
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const SwVfpRegister s13 = { 13 };
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const SwVfpRegister s14 = { 14 };
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const SwVfpRegister s15 = { 15 };
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const SwVfpRegister s16 = { 16 };
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const SwVfpRegister s17 = { 17 };
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const SwVfpRegister s18 = { 18 };
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const SwVfpRegister s19 = { 19 };
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const SwVfpRegister s20 = { 20 };
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const SwVfpRegister s21 = { 21 };
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const SwVfpRegister s22 = { 22 };
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const SwVfpRegister s23 = { 23 };
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const SwVfpRegister s24 = { 24 };
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const SwVfpRegister s25 = { 25 };
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const SwVfpRegister s26 = { 26 };
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const SwVfpRegister s27 = { 27 };
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const SwVfpRegister s28 = { 28 };
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const SwVfpRegister s29 = { 29 };
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const SwVfpRegister s30 = { 30 };
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const SwVfpRegister s31 = { 31 };
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extern DwVfpRegister d0;
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extern DwVfpRegister d1;
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extern DwVfpRegister d2;
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extern DwVfpRegister d3;
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extern DwVfpRegister d4;
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extern DwVfpRegister d5;
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extern DwVfpRegister d6;
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extern DwVfpRegister d7;
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extern DwVfpRegister d8;
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extern DwVfpRegister d9;
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extern DwVfpRegister d10;
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extern DwVfpRegister d11;
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extern DwVfpRegister d12;
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extern DwVfpRegister d13;
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extern DwVfpRegister d14;
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extern DwVfpRegister d15;
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const DwVfpRegister d0 = { 0 };
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const DwVfpRegister d1 = { 1 };
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const DwVfpRegister d2 = { 2 };
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const DwVfpRegister d3 = { 3 };
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const DwVfpRegister d4 = { 4 };
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const DwVfpRegister d5 = { 5 };
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const DwVfpRegister d6 = { 6 };
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const DwVfpRegister d7 = { 7 };
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const DwVfpRegister d8 = { 8 };
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const DwVfpRegister d9 = { 9 };
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const DwVfpRegister d10 = { 10 };
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const DwVfpRegister d11 = { 11 };
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const DwVfpRegister d12 = { 12 };
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const DwVfpRegister d13 = { 13 };
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const DwVfpRegister d14 = { 14 };
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const DwVfpRegister d15 = { 15 };
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// Coprocessor register
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@ -210,23 +209,24 @@ struct CRegister {
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};
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extern CRegister no_creg;
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extern CRegister cr0;
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extern CRegister cr1;
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extern CRegister cr2;
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extern CRegister cr3;
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extern CRegister cr4;
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extern CRegister cr5;
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extern CRegister cr6;
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extern CRegister cr7;
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extern CRegister cr8;
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extern CRegister cr9;
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extern CRegister cr10;
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extern CRegister cr11;
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extern CRegister cr12;
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extern CRegister cr13;
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extern CRegister cr14;
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extern CRegister cr15;
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const CRegister no_creg = { -1 };
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const CRegister cr0 = { 0 };
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const CRegister cr1 = { 1 };
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const CRegister cr2 = { 2 };
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const CRegister cr3 = { 3 };
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const CRegister cr4 = { 4 };
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const CRegister cr5 = { 5 };
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const CRegister cr6 = { 6 };
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const CRegister cr7 = { 7 };
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const CRegister cr8 = { 8 };
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const CRegister cr9 = { 9 };
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const CRegister cr10 = { 10 };
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const CRegister cr11 = { 11 };
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const CRegister cr12 = { 12 };
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const CRegister cr13 = { 13 };
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const CRegister cr14 = { 14 };
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const CRegister cr15 = { 15 };
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// Coprocessor number
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