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[mips][wasm-simd] Remove add horiz instructions

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Port: 430407cd2c

Bug: v8:6020
Change-Id: I9e4e3f21a1adc87f83ff7ebf6c157f9c453353e2
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2738894
Auto-Submit: Liu yu <liuyu@loongson.cn>
Reviewed-by: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Commit-Queue: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Cr-Commit-Position: refs/heads/master@{#73209}
This commit is contained in:
Liu Yu 2021-03-05 11:16:07 +08:00 committed by Commit Bot
parent 3bb25afa26
commit 0be03022f5
8 changed files with 0 additions and 82 deletions
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32
src/compiler/backend/mips/code-generator-mips.cc
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@ -3629,38 +3629,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ pckev_b(dst, kSimd128RegZero, kSimd128ScratchReg); __ pckev_b(dst, kSimd128RegZero, kSimd128ScratchReg);
break; break;
} }
case kMipsF32x4AddHoriz: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Simd128Register dst = i.OutputSimd128Register();
__ shf_w(kSimd128ScratchReg, src0, 0xB1); // 2 3 0 1 : 10110001 : 0xB1
__ shf_w(kSimd128RegZero, src1, 0xB1); // kSimd128RegZero as scratch
__ fadd_w(kSimd128ScratchReg, kSimd128ScratchReg, src0);
__ fadd_w(kSimd128RegZero, kSimd128RegZero, src1);
__ pckev_w(dst, kSimd128RegZero, kSimd128ScratchReg);
break;
}
case kMipsI32x4AddHoriz: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Simd128Register dst = i.OutputSimd128Register();
__ hadd_s_d(kSimd128ScratchReg, src0, src0);
__ hadd_s_d(kSimd128RegZero, src1, src1); // kSimd128RegZero as scratch
__ pckev_w(dst, kSimd128RegZero, kSimd128ScratchReg);
break;
}
case kMipsI16x8AddHoriz: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Simd128Register dst = i.OutputSimd128Register();
__ hadd_s_w(kSimd128ScratchReg, src0, src0);
__ hadd_s_w(kSimd128RegZero, src1, src1); // kSimd128RegZero as scratch
__ pckev_h(dst, kSimd128RegZero, kSimd128ScratchReg);
break;
}
} }
return kSuccess; return kSuccess;
} // NOLINT(readability/fn_size) } // NOLINT(readability/fn_size)

3
src/compiler/backend/mips/instruction-codes-mips.h
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@ -139,7 +139,6 @@ namespace compiler {
V(MipsI32x4ExtractLane) \ V(MipsI32x4ExtractLane) \
V(MipsI32x4ReplaceLane) \ V(MipsI32x4ReplaceLane) \
V(MipsI32x4Add) \ V(MipsI32x4Add) \
V(MipsI32x4AddHoriz) \
V(MipsI32x4Sub) \ V(MipsI32x4Sub) \
V(MipsF64x2Abs) \ V(MipsF64x2Abs) \
V(MipsF64x2Neg) \ V(MipsF64x2Neg) \
@ -209,7 +208,6 @@ namespace compiler {
V(MipsF32x4RecipApprox) \ V(MipsF32x4RecipApprox) \
V(MipsF32x4RecipSqrtApprox) \ V(MipsF32x4RecipSqrtApprox) \
V(MipsF32x4Add) \ V(MipsF32x4Add) \
V(MipsF32x4AddHoriz) \
V(MipsF32x4Sub) \ V(MipsF32x4Sub) \
V(MipsF32x4Mul) \ V(MipsF32x4Mul) \
V(MipsF32x4Div) \ V(MipsF32x4Div) \
@ -253,7 +251,6 @@ namespace compiler {
V(MipsI16x8ShrU) \ V(MipsI16x8ShrU) \
V(MipsI16x8Add) \ V(MipsI16x8Add) \
V(MipsI16x8AddSatS) \ V(MipsI16x8AddSatS) \
V(MipsI16x8AddHoriz) \
V(MipsI16x8Sub) \ V(MipsI16x8Sub) \
V(MipsI16x8SubSatS) \ V(MipsI16x8SubSatS) \
V(MipsI16x8Mul) \ V(MipsI16x8Mul) \

3
src/compiler/backend/mips/instruction-scheduler-mips.cc
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@ -89,7 +89,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMipsI64x2ExtMulHighI32x4U: case kMipsI64x2ExtMulHighI32x4U:
case kMipsF32x4Abs: case kMipsF32x4Abs:
case kMipsF32x4Add: case kMipsF32x4Add:
case kMipsF32x4AddHoriz:
case kMipsF32x4Eq: case kMipsF32x4Eq:
case kMipsF32x4ExtractLane: case kMipsF32x4ExtractLane:
case kMipsF32x4Le: case kMipsF32x4Le:
@ -135,7 +134,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMipsFloorWD: case kMipsFloorWD:
case kMipsFloorWS: case kMipsFloorWS:
case kMipsI16x8Add: case kMipsI16x8Add:
case kMipsI16x8AddHoriz:
case kMipsI16x8AddSatS: case kMipsI16x8AddSatS:
case kMipsI16x8AddSatU: case kMipsI16x8AddSatU:
case kMipsI16x8Eq: case kMipsI16x8Eq:
@ -179,7 +177,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMipsI32x4ExtAddPairwiseI16x8S: case kMipsI32x4ExtAddPairwiseI16x8S:
case kMipsI32x4ExtAddPairwiseI16x8U: case kMipsI32x4ExtAddPairwiseI16x8U:
case kMipsI32x4Add: case kMipsI32x4Add:
case kMipsI32x4AddHoriz:
case kMipsI32x4Eq: case kMipsI32x4Eq:
case kMipsI32x4ExtractLane: case kMipsI32x4ExtractLane:
case kMipsI32x4GeS: case kMipsI32x4GeS:

3
src/compiler/backend/mips/instruction-selector-mips.cc
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@ -2212,7 +2212,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I64x2ExtMulLowI32x4U, kMipsI64x2ExtMulLowI32x4U) \ V(I64x2ExtMulLowI32x4U, kMipsI64x2ExtMulLowI32x4U) \
V(I64x2ExtMulHighI32x4U, kMipsI64x2ExtMulHighI32x4U) \ V(I64x2ExtMulHighI32x4U, kMipsI64x2ExtMulHighI32x4U) \
V(F32x4Add, kMipsF32x4Add) \ V(F32x4Add, kMipsF32x4Add) \
V(F32x4AddHoriz, kMipsF32x4AddHoriz) \
V(F32x4Sub, kMipsF32x4Sub) \ V(F32x4Sub, kMipsF32x4Sub) \
V(F32x4Mul, kMipsF32x4Mul) \ V(F32x4Mul, kMipsF32x4Mul) \
V(F32x4Div, kMipsF32x4Div) \ V(F32x4Div, kMipsF32x4Div) \
@ -2223,7 +2222,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(F32x4Lt, kMipsF32x4Lt) \ V(F32x4Lt, kMipsF32x4Lt) \
V(F32x4Le, kMipsF32x4Le) \ V(F32x4Le, kMipsF32x4Le) \
V(I32x4Add, kMipsI32x4Add) \ V(I32x4Add, kMipsI32x4Add) \
V(I32x4AddHoriz, kMipsI32x4AddHoriz) \
V(I32x4Sub, kMipsI32x4Sub) \ V(I32x4Sub, kMipsI32x4Sub) \
V(I32x4Mul, kMipsI32x4Mul) \ V(I32x4Mul, kMipsI32x4Mul) \
V(I32x4MaxS, kMipsI32x4MaxS) \ V(I32x4MaxS, kMipsI32x4MaxS) \
@ -2245,7 +2243,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I16x8Add, kMipsI16x8Add) \ V(I16x8Add, kMipsI16x8Add) \
V(I16x8AddSatS, kMipsI16x8AddSatS) \ V(I16x8AddSatS, kMipsI16x8AddSatS) \
V(I16x8AddSatU, kMipsI16x8AddSatU) \ V(I16x8AddSatU, kMipsI16x8AddSatU) \
V(I16x8AddHoriz, kMipsI16x8AddHoriz) \
V(I16x8Sub, kMipsI16x8Sub) \ V(I16x8Sub, kMipsI16x8Sub) \
V(I16x8SubSatS, kMipsI16x8SubSatS) \ V(I16x8SubSatS, kMipsI16x8SubSatS) \
V(I16x8SubSatU, kMipsI16x8SubSatU) \ V(I16x8SubSatU, kMipsI16x8SubSatU) \

32
src/compiler/backend/mips64/code-generator-mips64.cc
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@ -3798,38 +3798,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ pckev_b(dst, dst, kSimd128ScratchReg); __ pckev_b(dst, dst, kSimd128ScratchReg);
break; break;
} }
case kMips64F32x4AddHoriz: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Simd128Register dst = i.OutputSimd128Register();
__ shf_w(kSimd128ScratchReg, src0, 0xB1); // 2 3 0 1 : 10110001 : 0xB1
__ shf_w(kSimd128RegZero, src1, 0xB1); // kSimd128RegZero as scratch
__ fadd_w(kSimd128ScratchReg, kSimd128ScratchReg, src0);
__ fadd_w(kSimd128RegZero, kSimd128RegZero, src1);
__ pckev_w(dst, kSimd128RegZero, kSimd128ScratchReg);
break;
}
case kMips64I32x4AddHoriz: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Simd128Register dst = i.OutputSimd128Register();
__ hadd_s_d(kSimd128ScratchReg, src0, src0);
__ hadd_s_d(kSimd128RegZero, src1, src1); // kSimd128RegZero as scratch
__ pckev_w(dst, kSimd128RegZero, kSimd128ScratchReg);
break;
}
case kMips64I16x8AddHoriz: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Simd128Register dst = i.OutputSimd128Register();
__ hadd_s_w(kSimd128ScratchReg, src0, src0);
__ hadd_s_w(kSimd128RegZero, src1, src1); // kSimd128RegZero as scratch
__ pckev_h(dst, kSimd128RegZero, kSimd128ScratchReg);
break;
}
} }
return kSuccess; return kSuccess;
} // NOLINT(readability/fn_size) } // NOLINT(readability/fn_size)

3
src/compiler/backend/mips64/instruction-codes-mips64.h
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@ -171,7 +171,6 @@ namespace compiler {
V(Mips64I32x4ExtractLane) \ V(Mips64I32x4ExtractLane) \
V(Mips64I32x4ReplaceLane) \ V(Mips64I32x4ReplaceLane) \
V(Mips64I32x4Add) \ V(Mips64I32x4Add) \
V(Mips64I32x4AddHoriz) \
V(Mips64I32x4Sub) \ V(Mips64I32x4Sub) \
V(Mips64F64x2Abs) \ V(Mips64F64x2Abs) \
V(Mips64F64x2Neg) \ V(Mips64F64x2Neg) \
@ -242,7 +241,6 @@ namespace compiler {
V(Mips64F32x4RecipApprox) \ V(Mips64F32x4RecipApprox) \
V(Mips64F32x4RecipSqrtApprox) \ V(Mips64F32x4RecipSqrtApprox) \
V(Mips64F32x4Add) \ V(Mips64F32x4Add) \
V(Mips64F32x4AddHoriz) \
V(Mips64F32x4Sub) \ V(Mips64F32x4Sub) \
V(Mips64F32x4Mul) \ V(Mips64F32x4Mul) \
V(Mips64F32x4Div) \ V(Mips64F32x4Div) \
@ -281,7 +279,6 @@ namespace compiler {
V(Mips64I16x8ShrU) \ V(Mips64I16x8ShrU) \
V(Mips64I16x8Add) \ V(Mips64I16x8Add) \
V(Mips64I16x8AddSatS) \ V(Mips64I16x8AddSatS) \
V(Mips64I16x8AddHoriz) \
V(Mips64I16x8Sub) \ V(Mips64I16x8Sub) \
V(Mips64I16x8SubSatS) \ V(Mips64I16x8SubSatS) \
V(Mips64I16x8Mul) \ V(Mips64I16x8Mul) \

3
src/compiler/backend/mips64/instruction-scheduler-mips64.cc
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@ -116,7 +116,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMips64ExtAddPairwise: case kMips64ExtAddPairwise:
case kMips64F32x4Abs: case kMips64F32x4Abs:
case kMips64F32x4Add: case kMips64F32x4Add:
case kMips64F32x4AddHoriz:
case kMips64F32x4Eq: case kMips64F32x4Eq:
case kMips64F32x4ExtractLane: case kMips64F32x4ExtractLane:
case kMips64F32x4Lt: case kMips64F32x4Lt:
@ -165,7 +164,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMips64FloorWD: case kMips64FloorWD:
case kMips64FloorWS: case kMips64FloorWS:
case kMips64I16x8Add: case kMips64I16x8Add:
case kMips64I16x8AddHoriz:
case kMips64I16x8AddSatS: case kMips64I16x8AddSatS:
case kMips64I16x8AddSatU: case kMips64I16x8AddSatU:
case kMips64I16x8Eq: case kMips64I16x8Eq:
@ -203,7 +201,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMips64I16x8BitMask: case kMips64I16x8BitMask:
case kMips64I16x8Q15MulRSatS: case kMips64I16x8Q15MulRSatS:
case kMips64I32x4Add: case kMips64I32x4Add:
case kMips64I32x4AddHoriz:
case kMips64I32x4Eq: case kMips64I32x4Eq:
case kMips64I32x4ExtractLane: case kMips64I32x4ExtractLane:
case kMips64I32x4GeS: case kMips64I32x4GeS:

3
src/compiler/backend/mips64/instruction-selector-mips64.cc
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@ -2942,7 +2942,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I64x2GtS, kMips64I64x2GtS) \ V(I64x2GtS, kMips64I64x2GtS) \
V(I64x2GeS, kMips64I64x2GeS) \ V(I64x2GeS, kMips64I64x2GeS) \
V(F32x4Add, kMips64F32x4Add) \ V(F32x4Add, kMips64F32x4Add) \
V(F32x4AddHoriz, kMips64F32x4AddHoriz) \
V(F32x4Sub, kMips64F32x4Sub) \ V(F32x4Sub, kMips64F32x4Sub) \
V(F32x4Mul, kMips64F32x4Mul) \ V(F32x4Mul, kMips64F32x4Mul) \
V(F32x4Div, kMips64F32x4Div) \ V(F32x4Div, kMips64F32x4Div) \
@ -2953,7 +2952,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(F32x4Lt, kMips64F32x4Lt) \ V(F32x4Lt, kMips64F32x4Lt) \
V(F32x4Le, kMips64F32x4Le) \ V(F32x4Le, kMips64F32x4Le) \
V(I32x4Add, kMips64I32x4Add) \ V(I32x4Add, kMips64I32x4Add) \
V(I32x4AddHoriz, kMips64I32x4AddHoriz) \
V(I32x4Sub, kMips64I32x4Sub) \ V(I32x4Sub, kMips64I32x4Sub) \
V(I32x4Mul, kMips64I32x4Mul) \ V(I32x4Mul, kMips64I32x4Mul) \
V(I32x4MaxS, kMips64I32x4MaxS) \ V(I32x4MaxS, kMips64I32x4MaxS) \
@ -2970,7 +2968,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I16x8Add, kMips64I16x8Add) \ V(I16x8Add, kMips64I16x8Add) \
V(I16x8AddSatS, kMips64I16x8AddSatS) \ V(I16x8AddSatS, kMips64I16x8AddSatS) \
V(I16x8AddSatU, kMips64I16x8AddSatU) \ V(I16x8AddSatU, kMips64I16x8AddSatU) \
V(I16x8AddHoriz, kMips64I16x8AddHoriz) \
V(I16x8Sub, kMips64I16x8Sub) \ V(I16x8Sub, kMips64I16x8Sub) \
V(I16x8SubSatS, kMips64I16x8SubSatS) \ V(I16x8SubSatS, kMips64I16x8SubSatS) \
V(I16x8SubSatU, kMips64I16x8SubSatU) \ V(I16x8SubSatU, kMips64I16x8SubSatU) \