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[riscv64] Use shift register when shift amount is too large

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Change-Id: Ib68766bf88624bfdad272680ce9e1180d241adf0
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3556927
Reviewed-by: ji qiu <qiuji@iscas.ac.cn>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#79664}
This commit is contained in:
Lu Yahan 2022-03-29 11:39:09 +08:00 committed by V8 LUCI CQ
parent 4fbe840818
commit 0ca7f58089
1 changed files with 30 additions and 12 deletions
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42
src/wasm/baseline/riscv64/liftoff-assembler-riscv64.h
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@ -1300,23 +1300,41 @@ I64_BINOP_I(xor, Xor)
LiftoffRegister dst, LiftoffRegister src, Register amount) { \
instruction(dst.gp(), src.gp(), amount); \
}
#define I64_SHIFTOP_I(name, instruction) \
void LiftoffAssembler::emit_i64_##name##i(LiftoffRegister dst, \
LiftoffRegister src, int amount) { \
DCHECK(is_uint6(amount)); \
instruction(dst.gp(), src.gp(), amount); \
}
I64_SHIFTOP(shl, sll)
I64_SHIFTOP(sar, sra)
I64_SHIFTOP(shr, srl)
I64_SHIFTOP_I(shl, slli)
I64_SHIFTOP_I(sar, srai)
I64_SHIFTOP_I(shr, srli)
#undef I64_SHIFTOP
#undef I64_SHIFTOP_I
void LiftoffAssembler::emit_i64_shli(LiftoffRegister dst, LiftoffRegister src,
int amount) {
if (is_uint6(amount)) {
slli(dst.gp(), src.gp(), amount);
} else {
li(kScratchReg, amount);
sll(dst.gp(), src.gp(), kScratchReg);
}
}
void LiftoffAssembler::emit_i64_sari(LiftoffRegister dst, LiftoffRegister src,
int amount) {
if (is_uint6(amount)) {
srai(dst.gp(), src.gp(), amount);
} else {
li(kScratchReg, amount);
sra(dst.gp(), src.gp(), kScratchReg);
}
}
void LiftoffAssembler::emit_i64_shri(LiftoffRegister dst, LiftoffRegister src,
int amount) {
if (is_uint6(amount)) {
srli(dst.gp(), src.gp(), amount);
} else {
li(kScratchReg, amount);
srl(dst.gp(), src.gp(), kScratchReg);
}
}
void LiftoffAssembler::emit_i64_addi(LiftoffRegister dst, LiftoffRegister lhs,
int64_t imm) {