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[mips] Fix Float32Neg and Float64Neg tests on target

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These tests fail since instructions were implemented in Liftoff.
Problem was with NaN cases, where additional job has to be done on
MIPS r2, r1 and Longsoon.

Change-Id: Id02462aa08e79b03d66b5083b81f19dc1c88cc3e
Reviewed-on: https://chromium-review.googlesource.com/1015001
Reviewed-by: Ivica Bogosavljevic <ivica.bogosavljevic@mips.com>
Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@mips.com>
Cr-Commit-Position: refs/heads/master@{#52647}
This commit is contained in:
sreten.kovacevic 2018-04-17 16:00:14 +02:00 committed by Commit Bot
parent eb4ebf98c9
commit 0cd4b3d69d
3 changed files with 18 additions and 5 deletions
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3
src/mips/macro-assembler-mips.cc
View File

@ -1745,7 +1745,8 @@ void TurboAssembler::Neg_d(FPURegister fd, FPURegister fs) {
// while the sign has to be changed separately.
neg_d(fd, fs); // In delay slot.
bind(&is_nan);
Mfhc1(scratch1, fs);
Move(fd, fs);
Mfhc1(scratch1, fd);
li(scratch2, HeapNumber::kSignMask);
Xor(scratch1, scratch1, scratch2);
Mthc1(scratch1, fd);

10
src/wasm/baseline/mips/liftoff-assembler-mips.h
View File

@ -669,6 +669,14 @@ void LiftoffAssembler::emit_i64_shr(LiftoffRegister dst, LiftoffRegister src,
&TurboAssembler::ShrPair, pinned);
}
void LiftoffAssembler::emit_f32_neg(DoubleRegister dst, DoubleRegister src) {
TurboAssembler::Neg_s(dst, src);
}
void LiftoffAssembler::emit_f64_neg(DoubleRegister dst, DoubleRegister src) {
TurboAssembler::Neg_d(dst, src);
}
#define FP_BINOP(name, instruction) \
void LiftoffAssembler::emit_##name(DoubleRegister dst, DoubleRegister lhs, \
DoubleRegister rhs) { \
@ -684,7 +692,6 @@ FP_BINOP(f32_sub, sub_s)
FP_BINOP(f32_mul, mul_s)
FP_BINOP(f32_div, div_s)
FP_UNOP(f32_abs, abs_s)
FP_UNOP(f32_neg, neg_s)
FP_UNOP(f32_ceil, Ceil_s_s)
FP_UNOP(f32_floor, Floor_s_s)
FP_UNOP(f32_trunc, Trunc_s_s)
@ -695,7 +702,6 @@ FP_BINOP(f64_sub, sub_d)
FP_BINOP(f64_mul, mul_d)
FP_BINOP(f64_div, div_d)
FP_UNOP(f64_abs, abs_d)
FP_UNOP(f64_neg, neg_d)
FP_UNOP(f64_sqrt, sqrt_d)
#undef FP_BINOP

10
src/wasm/baseline/mips64/liftoff-assembler-mips64.h
View File

@ -544,6 +544,14 @@ I64_SHIFTOP(shr, dsrlv)
#undef I64_SHIFTOP
void LiftoffAssembler::emit_f32_neg(DoubleRegister dst, DoubleRegister src) {
TurboAssembler::Neg_s(dst, src);
}
void LiftoffAssembler::emit_f64_neg(DoubleRegister dst, DoubleRegister src) {
TurboAssembler::Neg_d(dst, src);
}
#define FP_BINOP(name, instruction) \
void LiftoffAssembler::emit_##name(DoubleRegister dst, DoubleRegister lhs, \
DoubleRegister rhs) { \
@ -559,7 +567,6 @@ FP_BINOP(f32_sub, sub_s)
FP_BINOP(f32_mul, mul_s)
FP_BINOP(f32_div, div_s)
FP_UNOP(f32_abs, abs_s)
FP_UNOP(f32_neg, neg_s)
FP_UNOP(f32_ceil, Ceil_s_s)
FP_UNOP(f32_floor, Floor_s_s)
FP_UNOP(f32_trunc, Trunc_s_s)
@ -570,7 +577,6 @@ FP_BINOP(f64_sub, sub_d)
FP_BINOP(f64_mul, mul_d)
FP_BINOP(f64_div, div_d)
FP_UNOP(f64_abs, abs_d)
FP_UNOP(f64_neg, neg_d)
FP_UNOP(f64_ceil, Ceil_d_d)
FP_UNOP(f64_floor, Floor_d_d)
FP_UNOP(f64_trunc, Trunc_d_d)