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[riscv] Fix cctest/test-assembler-riscv*/RISCV_UTEST_FLOAT_WIDENING_vfwmacc_vf.

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Correct the arguments for std::fma() to double as the instruction expects
both addend and destination are 2*SEW bits wide. Addressed corresponding
implementation in the simulator as well.

R=qiuji@iscas.ac.cn

Change-Id: Ib3963a61c00ee9dc73af019574a1665de406cc32
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3878448
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#83353}
This commit is contained in:
Ting Chou 2022-09-07 14:24:09 +08:00 committed by V8 LUCI CQ
parent d4fa48b726
commit 0d85646664
3 changed files with 46 additions and 26 deletions
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20
src/execution/riscv/simulator-riscv.cc
View File

@ -867,7 +867,7 @@ struct type_sew_t<128> {
double vs2 = vs2_is_widen \
? Rvvelt<double>(rvv_vs2_reg(), i) \
: static_cast<double>(Rvvelt<float>(rvv_vs2_reg(), i)); \
double vs3 = static_cast<double>(Rvvelt<float>(rvv_vd_reg(), i)); \
double vs3 = Rvvelt<double>(rvv_vd_reg(), i); \
BODY32; \
break; \
} \
@ -892,7 +892,7 @@ struct type_sew_t<128> {
? static_cast<double>(Rvvelt<double>(rvv_vs2_reg(), i)) \
: static_cast<double>(Rvvelt<float>(rvv_vs2_reg(), i)); \
double vs1 = static_cast<double>(Rvvelt<float>(rvv_vs1_reg(), i)); \
double vs3 = static_cast<double>(Rvvelt<float>(rvv_vd_reg(), i)); \
double vs3 = Rvvelt<double>(rvv_vd_reg(), i); \
BODY32; \
break; \
} \
@ -6921,19 +6921,19 @@ void Simulator::DecodeRvvFVV() {
break;
case RO_V_VFWMACC_VV:
RVV_VI_CHECK_DSS(true);
RVV_VI_VFP_VV_LOOP_WIDEN({RVV_VI_VFP_FMA(float, vs2, vs1, vs3)}, false)
RVV_VI_VFP_VV_LOOP_WIDEN({RVV_VI_VFP_FMA(double, vs2, vs1, vs3)}, false)
break;
case RO_V_VFWNMACC_VV:
RVV_VI_CHECK_DSS(true);
RVV_VI_VFP_VV_LOOP_WIDEN({RVV_VI_VFP_FMA(float, -vs2, vs1, -vs3)}, false)
RVV_VI_VFP_VV_LOOP_WIDEN({RVV_VI_VFP_FMA(double, -vs2, vs1, -vs3)}, false)
break;
case RO_V_VFWMSAC_VV:
RVV_VI_CHECK_DSS(true);
RVV_VI_VFP_VV_LOOP_WIDEN({RVV_VI_VFP_FMA(float, vs2, vs1, -vs3)}, false)
RVV_VI_VFP_VV_LOOP_WIDEN({RVV_VI_VFP_FMA(double, vs2, vs1, -vs3)}, false)
break;
case RO_V_VFWNMSAC_VV:
RVV_VI_CHECK_DSS(true);
RVV_VI_VFP_VV_LOOP_WIDEN({RVV_VI_VFP_FMA(float, -vs2, vs1, +vs3)}, false)
RVV_VI_VFP_VV_LOOP_WIDEN({RVV_VI_VFP_FMA(double, -vs2, vs1, +vs3)}, false)
break;
case RO_V_VFMV_FS:
switch (rvv_vsew()) {
@ -7071,19 +7071,19 @@ void Simulator::DecodeRvvFVF() {
break;
case RO_V_VFWMACC_VF:
RVV_VI_CHECK_DSS(true);
RVV_VI_VFP_VF_LOOP_WIDEN({RVV_VI_VFP_FMA(float, vs2, fs1, vs3)}, false)
RVV_VI_VFP_VF_LOOP_WIDEN({RVV_VI_VFP_FMA(double, vs2, fs1, vs3)}, false)
break;
case RO_V_VFWNMACC_VF:
RVV_VI_CHECK_DSS(true);
RVV_VI_VFP_VF_LOOP_WIDEN({RVV_VI_VFP_FMA(float, -vs2, fs1, -vs3)}, false)
RVV_VI_VFP_VF_LOOP_WIDEN({RVV_VI_VFP_FMA(double, -vs2, fs1, -vs3)}, false)
break;
case RO_V_VFWMSAC_VF:
RVV_VI_CHECK_DSS(true);
RVV_VI_VFP_VF_LOOP_WIDEN({RVV_VI_VFP_FMA(float, vs2, fs1, -vs3)}, false)
RVV_VI_VFP_VF_LOOP_WIDEN({RVV_VI_VFP_FMA(double, vs2, fs1, -vs3)}, false)
break;
case RO_V_VFWNMSAC_VF:
RVV_VI_CHECK_DSS(true);
RVV_VI_VFP_VF_LOOP_WIDEN({RVV_VI_VFP_FMA(float, -vs2, fs1, vs3)}, false)
RVV_VI_VFP_VF_LOOP_WIDEN({RVV_VI_VFP_FMA(double, -vs2, fs1, vs3)}, false)
break;
default:
UNSUPPORTED_RISCV();

26
test/cctest/test-assembler-riscv32.cc
View File

@ -2145,6 +2145,11 @@ UTEST_RVV_VFW_VF_FORM_WITH_OP(vfwmul_vf, *, false, is_invalid_fmul)
for (float rs1_fval : array) { \
for (float rs2_fval : array) { \
for (float rs3_fval : array) { \
double rs1_dval = base::bit_cast<double>( \
(uint64_t)base::bit_cast<uint32_t>(rs1_fval) << 32 | \
base::bit_cast<uint32_t>(rs1_fval)); \
double rs2_dval = static_cast<double>(rs2_fval); \
double rs3_dval = static_cast<double>(rs3_fval); \
double res = \
GenAndRunTest<double, float>(rs1_fval, rs2_fval, rs3_fval, fn); \
CHECK_DOUBLE_EQ((expect_res), res); \
@ -2170,6 +2175,11 @@ UTEST_RVV_VFW_VF_FORM_WITH_OP(vfwmul_vf, *, false, is_invalid_fmul)
for (float rs1_fval : array) { \
for (float rs2_fval : array) { \
for (float rs3_fval : array) { \
double rs1_dval = base::bit_cast<double>( \
(uint64_t)base::bit_cast<uint32_t>(rs1_fval) << 32 | \
base::bit_cast<uint32_t>(rs1_fval)); \
double rs2_dval = static_cast<double>(rs2_fval); \
double rs3_dval = static_cast<double>(rs3_fval); \
double res = \
GenAndRunTest<double, float>(rs1_fval, rs2_fval, rs3_fval, fn); \
CHECK_DOUBLE_EQ((expect_res), res); \
@ -2180,21 +2190,21 @@ UTEST_RVV_VFW_VF_FORM_WITH_OP(vfwmul_vf, *, false, is_invalid_fmul)
#define ARRAY_FLOAT compiler::ValueHelper::GetVector<float>()
UTEST_RVV_VFW_FMA_VV_FORM_WITH_RES(vfwmacc_vv, ARRAY_FLOAT,
std::fma(rs2_fval, rs3_fval, rs1_fval))
std::fma(rs2_dval, rs3_dval, rs1_dval))
UTEST_RVV_VFW_FMA_VF_FORM_WITH_RES(vfwmacc_vf, ARRAY_FLOAT,
std::fma(rs2_fval, rs3_fval, rs1_fval))
std::fma(rs2_dval, rs3_dval, rs1_dval))
UTEST_RVV_VFW_FMA_VV_FORM_WITH_RES(vfwnmacc_vv, ARRAY_FLOAT,
std::fma(rs2_fval, -rs3_fval, -rs1_fval))
std::fma(rs2_dval, -rs3_dval, -rs1_dval))
UTEST_RVV_VFW_FMA_VF_FORM_WITH_RES(vfwnmacc_vf, ARRAY_FLOAT,
std::fma(rs2_fval, -rs3_fval, -rs1_fval))
std::fma(rs2_dval, -rs3_dval, -rs1_dval))
UTEST_RVV_VFW_FMA_VV_FORM_WITH_RES(vfwmsac_vv, ARRAY_FLOAT,
std::fma(rs2_fval, rs3_fval, -rs1_fval))
std::fma(rs2_dval, rs3_dval, -rs1_dval))
UTEST_RVV_VFW_FMA_VF_FORM_WITH_RES(vfwmsac_vf, ARRAY_FLOAT,
std::fma(rs2_fval, rs3_fval, -rs1_fval))
std::fma(rs2_dval, rs3_dval, -rs1_dval))
UTEST_RVV_VFW_FMA_VV_FORM_WITH_RES(vfwnmsac_vv, ARRAY_FLOAT,
std::fma(rs2_fval, -rs3_fval, rs1_fval))
std::fma(rs2_dval, -rs3_dval, rs1_dval))
UTEST_RVV_VFW_FMA_VF_FORM_WITH_RES(vfwnmsac_vf, ARRAY_FLOAT,
std::fma(rs2_fval, -rs3_fval, rs1_fval))
std::fma(rs2_dval, -rs3_dval, rs1_dval))
#undef ARRAY_FLOAT
#undef UTEST_RVV_VFW_FMA_VV_FORM_WITH_RES

26
test/cctest/test-assembler-riscv64.cc
View File

@ -2409,6 +2409,11 @@ UTEST_RVV_VFW_VF_FORM_WITH_OP(vfwmul_vf, *, false, is_invalid_fmul)
for (float rs1_fval : array) { \
for (float rs2_fval : array) { \
for (float rs3_fval : array) { \
double rs1_dval = base::bit_cast<double>( \
(uint64_t)base::bit_cast<uint32_t>(rs1_fval) << 32 | \
base::bit_cast<uint32_t>(rs1_fval)); \
double rs2_dval = static_cast<double>(rs2_fval); \
double rs3_dval = static_cast<double>(rs3_fval); \
double res = \
GenAndRunTest<double, float>(rs1_fval, rs2_fval, rs3_fval, fn); \
CHECK_DOUBLE_EQ((expect_res), res); \
@ -2434,6 +2439,11 @@ UTEST_RVV_VFW_VF_FORM_WITH_OP(vfwmul_vf, *, false, is_invalid_fmul)
for (float rs1_fval : array) { \
for (float rs2_fval : array) { \
for (float rs3_fval : array) { \
double rs1_dval = base::bit_cast<double>( \
(uint64_t)base::bit_cast<uint32_t>(rs1_fval) << 32 | \
base::bit_cast<uint32_t>(rs1_fval)); \
double rs2_dval = static_cast<double>(rs2_fval); \
double rs3_dval = static_cast<double>(rs3_fval); \
double res = \
GenAndRunTest<double, float>(rs1_fval, rs2_fval, rs3_fval, fn); \
CHECK_DOUBLE_EQ((expect_res), res); \
@ -2444,21 +2454,21 @@ UTEST_RVV_VFW_VF_FORM_WITH_OP(vfwmul_vf, *, false, is_invalid_fmul)
#define ARRAY_FLOAT compiler::ValueHelper::GetVector<float>()
UTEST_RVV_VFW_FMA_VV_FORM_WITH_RES(vfwmacc_vv, ARRAY_FLOAT,
std::fma(rs2_fval, rs3_fval, rs1_fval))
std::fma(rs2_dval, rs3_dval, rs1_dval))
UTEST_RVV_VFW_FMA_VF_FORM_WITH_RES(vfwmacc_vf, ARRAY_FLOAT,
std::fma(rs2_fval, rs3_fval, rs1_fval))
std::fma(rs2_dval, rs3_dval, rs1_dval))
UTEST_RVV_VFW_FMA_VV_FORM_WITH_RES(vfwnmacc_vv, ARRAY_FLOAT,
std::fma(rs2_fval, -rs3_fval, -rs1_fval))
std::fma(rs2_dval, -rs3_dval, -rs1_dval))
UTEST_RVV_VFW_FMA_VF_FORM_WITH_RES(vfwnmacc_vf, ARRAY_FLOAT,
std::fma(rs2_fval, -rs3_fval, -rs1_fval))
std::fma(rs2_dval, -rs3_dval, -rs1_dval))
UTEST_RVV_VFW_FMA_VV_FORM_WITH_RES(vfwmsac_vv, ARRAY_FLOAT,
std::fma(rs2_fval, rs3_fval, -rs1_fval))
std::fma(rs2_dval, rs3_dval, -rs1_dval))
UTEST_RVV_VFW_FMA_VF_FORM_WITH_RES(vfwmsac_vf, ARRAY_FLOAT,
std::fma(rs2_fval, rs3_fval, -rs1_fval))
std::fma(rs2_dval, rs3_dval, -rs1_dval))
UTEST_RVV_VFW_FMA_VV_FORM_WITH_RES(vfwnmsac_vv, ARRAY_FLOAT,
std::fma(rs2_fval, -rs3_fval, rs1_fval))
std::fma(rs2_dval, -rs3_dval, rs1_dval))
UTEST_RVV_VFW_FMA_VF_FORM_WITH_RES(vfwnmsac_vf, ARRAY_FLOAT,
std::fma(rs2_fval, -rs3_fval, rs1_fval))
std::fma(rs2_dval, -rs3_dval, rs1_dval))
#undef ARRAY_FLOAT
#undef UTEST_RVV_VFW_FMA_VV_FORM_WITH_RES