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MIPS: Rename BranchF functions.

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Review URL: https://codereview.chromium.org/1052653003

Cr-Commit-Position: refs/heads/master@{#27575}
This commit is contained in:
balazs.kilvady 2015-04-01 11:39:22 -07:00 committed by Commit bot
parent 94506cc3c2
commit 0f086d1412
6 changed files with 84 additions and 92 deletions
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8
src/compiler/mips/code-generator-mips.cc
View File

@ -858,8 +858,8 @@ void CodeGenerator::AssembleArchBranch(Instruction* instr, BranchInfo* branch) {
UNSUPPORTED_COND(kMips64CmpS, branch->condition);
}
Label* nan = acceptNaN ? tlabel : flabel;
__ BranchFS(tlabel, nan, cc, i.InputSingleRegister(0),
i.InputSingleRegister(1));
__ BranchF32(tlabel, nan, cc, i.InputSingleRegister(0),
i.InputSingleRegister(1));
if (!branch->fallthru) __ Branch(flabel); // no fallthru to flabel.
@ -871,8 +871,8 @@ void CodeGenerator::AssembleArchBranch(Instruction* instr, BranchInfo* branch) {
UNSUPPORTED_COND(kMips64CmpD, branch->condition);
}
Label* nan = acceptNaN ? tlabel : flabel;
__ BranchF(tlabel, nan, cc, i.InputDoubleRegister(0),
i.InputDoubleRegister(1));
__ BranchF64(tlabel, nan, cc, i.InputDoubleRegister(0),
i.InputDoubleRegister(1));
if (!branch->fallthru) __ Branch(flabel); // no fallthru to flabel.

8
src/compiler/mips64/code-generator-mips64.cc
View File

@ -923,8 +923,8 @@ void CodeGenerator::AssembleArchBranch(Instruction* instr, BranchInfo* branch) {
UNSUPPORTED_COND(kMips64CmpS, branch->condition);
}
Label* nan = acceptNaN ? tlabel : flabel;
__ BranchFS(tlabel, nan, cc, i.InputSingleRegister(0),
i.InputSingleRegister(1));
__ BranchF32(tlabel, nan, cc, i.InputSingleRegister(0),
i.InputSingleRegister(1));
if (!branch->fallthru) __ Branch(flabel); // no fallthru to flabel.
@ -936,8 +936,8 @@ void CodeGenerator::AssembleArchBranch(Instruction* instr, BranchInfo* branch) {
UNSUPPORTED_COND(kMips64CmpD, branch->condition);
}
Label* nan = acceptNaN ? tlabel : flabel;
__ BranchF(tlabel, nan, cc, i.InputDoubleRegister(0),
i.InputDoubleRegister(1));
__ BranchF64(tlabel, nan, cc, i.InputDoubleRegister(0),
i.InputDoubleRegister(1));
if (!branch->fallthru) __ Branch(flabel); // no fallthru to flabel.
} else {

20
src/mips/macro-assembler-mips.cc
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@ -1430,9 +1430,9 @@ void MacroAssembler::Mfhc1(Register rt, FPURegister fs) {
}
void MacroAssembler::BranchFSize(SecondaryField sizeField, Label* target,
Label* nan, Condition cc, FPURegister cmp1,
FPURegister cmp2, BranchDelaySlot bd) {
void MacroAssembler::BranchFCommon(SecondaryField sizeField, Label* target,
Label* nan, Condition cc, FPURegister cmp1,
FPURegister cmp2, BranchDelaySlot bd) {
BlockTrampolinePoolScope block_trampoline_pool(this);
if (cc == al) {
Branch(bd, target);
@ -1551,20 +1551,6 @@ void MacroAssembler::BranchFSize(SecondaryField sizeField, Label* target,
}
void MacroAssembler::BranchF(Label* target, Label* nan, Condition cc,
FPURegister cmp1, FPURegister cmp2,
BranchDelaySlot bd) {
BranchFSize(D, target, nan, cc, cmp1, cmp2, bd);
}
void MacroAssembler::BranchFS(Label* target, Label* nan, Condition cc,
FPURegister cmp1, FPURegister cmp2,
BranchDelaySlot bd) {
BranchFSize(S, target, nan, cc, cmp1, cmp2, bd);
}
void MacroAssembler::FmoveLow(FPURegister dst, Register src_low) {
if (IsFp64Mode()) {
DCHECK(!src_low.is(at));

60
src/mips/macro-assembler-mips.h
View File

@ -772,33 +772,38 @@ class MacroAssembler: public Assembler {
void Mfhc1(Register rt, FPURegister fs);
// Wrapper functions for the different cmp/branch types.
void BranchFSize(SecondaryField sizeField, Label* target, Label* nan,
Condition cc, FPURegister cmp1, FPURegister cmp2,
BranchDelaySlot bd = PROTECT);
void BranchF(Label* target,
Label* nan,
Condition cc,
FPURegister cmp1,
FPURegister cmp2,
BranchDelaySlot bd = PROTECT);
void BranchFS(Label* target, Label* nan, Condition cc, FPURegister cmp1,
FPURegister cmp2, BranchDelaySlot bd = PROTECT);
// Alternate (inline) version for better readability with USE_DELAY_SLOT.
inline void BranchF(BranchDelaySlot bd,
Label* target,
Label* nan,
Condition cc,
FPURegister cmp1,
FPURegister cmp2) {
BranchF(target, nan, cc, cmp1, cmp2, bd);
inline void BranchF32(Label* target, Label* nan, Condition cc,
FPURegister cmp1, FPURegister cmp2,
BranchDelaySlot bd = PROTECT) {
BranchFCommon(S, target, nan, cc, cmp1, cmp2, bd);
}
inline void BranchFS(BranchDelaySlot bd, Label* target, Label* nan,
Condition cc, FPURegister cmp1, FPURegister cmp2) {
BranchFS(target, nan, cc, cmp1, cmp2, bd);
inline void BranchF64(Label* target, Label* nan, Condition cc,
FPURegister cmp1, FPURegister cmp2,
BranchDelaySlot bd = PROTECT) {
BranchFCommon(D, target, nan, cc, cmp1, cmp2, bd);
}
// Alternate (inline) version for better readability with USE_DELAY_SLOT.
inline void BranchF64(BranchDelaySlot bd, Label* target, Label* nan,
Condition cc, FPURegister cmp1, FPURegister cmp2) {
BranchF64(target, nan, cc, cmp1, cmp2, bd);
}
inline void BranchF32(BranchDelaySlot bd, Label* target, Label* nan,
Condition cc, FPURegister cmp1, FPURegister cmp2) {
BranchF32(target, nan, cc, cmp1, cmp2, bd);
}
// Alias functions for backward compatibility.
inline void BranchF(Label* target, Label* nan, Condition cc, FPURegister cmp1,
FPURegister cmp2, BranchDelaySlot bd = PROTECT) {
BranchF64(target, nan, cc, cmp1, cmp2, bd);
}
inline void BranchF(BranchDelaySlot bd, Label* target, Label* nan,
Condition cc, FPURegister cmp1, FPURegister cmp2) {
BranchF64(bd, target, nan, cc, cmp1, cmp2);
}
// Truncates a double using a specific rounding mode, and writes the value
@ -1632,6 +1637,11 @@ const Operand& rt = Operand(zero_reg), BranchDelaySlot bd = PROTECT
void Jr(Label* L, BranchDelaySlot bdslot);
void Jalr(Label* L, BranchDelaySlot bdslot);
// Common implementation of BranchF functions for the different formats.
void BranchFCommon(SecondaryField sizeField, Label* target, Label* nan,
Condition cc, FPURegister cmp1, FPURegister cmp2,
BranchDelaySlot bd = PROTECT);
// Helper functions for generating invokes.
void InvokePrologue(const ParameterCount& expected,
const ParameterCount& actual,

20
src/mips64/macro-assembler-mips64.cc
View File

@ -1629,9 +1629,9 @@ void MacroAssembler::Madd_d(FPURegister fd, FPURegister fr, FPURegister fs,
}
void MacroAssembler::BranchFSize(SecondaryField sizeField, Label* target,
Label* nan, Condition cc, FPURegister cmp1,
FPURegister cmp2, BranchDelaySlot bd) {
void MacroAssembler::BranchFCommon(SecondaryField sizeField, Label* target,
Label* nan, Condition cc, FPURegister cmp1,
FPURegister cmp2, BranchDelaySlot bd) {
BlockTrampolinePoolScope block_trampoline_pool(this);
if (cc == al) {
Branch(bd, target);
@ -1749,20 +1749,6 @@ void MacroAssembler::BranchFSize(SecondaryField sizeField, Label* target,
}
void MacroAssembler::BranchF(Label* target, Label* nan, Condition cc,
FPURegister cmp1, FPURegister cmp2,
BranchDelaySlot bd) {
BranchFSize(D, target, nan, cc, cmp1, cmp2, bd);
}
void MacroAssembler::BranchFS(Label* target, Label* nan, Condition cc,
FPURegister cmp1, FPURegister cmp2,
BranchDelaySlot bd) {
BranchFSize(S, target, nan, cc, cmp1, cmp2, bd);
}
void MacroAssembler::FmoveLow(FPURegister dst, Register src_low) {
DCHECK(!src_low.is(at));
mfhc1(at, dst);

60
src/mips64/macro-assembler-mips64.h
View File

@ -802,33 +802,38 @@ class MacroAssembler: public Assembler {
FPURegister scratch);
// Wrapper functions for the different cmp/branch types.
void BranchFSize(SecondaryField sizeField, Label* target, Label* nan,
Condition cc, FPURegister cmp1, FPURegister cmp2,
BranchDelaySlot bd = PROTECT);
void BranchF(Label* target,
Label* nan,
Condition cc,
FPURegister cmp1,
FPURegister cmp2,
BranchDelaySlot bd = PROTECT);
void BranchFS(Label* target, Label* nan, Condition cc, FPURegister cmp1,
FPURegister cmp2, BranchDelaySlot bd = PROTECT);
// Alternate (inline) version for better readability with USE_DELAY_SLOT.
inline void BranchF(BranchDelaySlot bd,
Label* target,
Label* nan,
Condition cc,
FPURegister cmp1,
FPURegister cmp2) {
BranchF(target, nan, cc, cmp1, cmp2, bd);
inline void BranchF32(Label* target, Label* nan, Condition cc,
FPURegister cmp1, FPURegister cmp2,
BranchDelaySlot bd = PROTECT) {
BranchFCommon(S, target, nan, cc, cmp1, cmp2, bd);
}
inline void BranchFS(BranchDelaySlot bd, Label* target, Label* nan,
Condition cc, FPURegister cmp1, FPURegister cmp2) {
BranchFS(target, nan, cc, cmp1, cmp2, bd);
inline void BranchF64(Label* target, Label* nan, Condition cc,
FPURegister cmp1, FPURegister cmp2,
BranchDelaySlot bd = PROTECT) {
BranchFCommon(D, target, nan, cc, cmp1, cmp2, bd);
}
// Alternate (inline) version for better readability with USE_DELAY_SLOT.
inline void BranchF64(BranchDelaySlot bd, Label* target, Label* nan,
Condition cc, FPURegister cmp1, FPURegister cmp2) {
BranchF64(target, nan, cc, cmp1, cmp2, bd);
}
inline void BranchF32(BranchDelaySlot bd, Label* target, Label* nan,
Condition cc, FPURegister cmp1, FPURegister cmp2) {
BranchF32(target, nan, cc, cmp1, cmp2, bd);
}
// Alias functions for backward compatibility.
inline void BranchF(Label* target, Label* nan, Condition cc, FPURegister cmp1,
FPURegister cmp2, BranchDelaySlot bd = PROTECT) {
BranchF64(target, nan, cc, cmp1, cmp2, bd);
}
inline void BranchF(BranchDelaySlot bd, Label* target, Label* nan,
Condition cc, FPURegister cmp1, FPURegister cmp2) {
BranchF64(bd, target, nan, cc, cmp1, cmp2);
}
// Truncates a double using a specific rounding mode, and writes the value
@ -1701,6 +1706,11 @@ const Operand& rt = Operand(zero_reg), BranchDelaySlot bd = PROTECT
void Jr(Label* L, BranchDelaySlot bdslot);
void Jalr(Label* L, BranchDelaySlot bdslot);
// Common implementation of BranchF functions for the different formats.
void BranchFCommon(SecondaryField sizeField, Label* target, Label* nan,
Condition cc, FPURegister cmp1, FPURegister cmp2,
BranchDelaySlot bd = PROTECT);
// Helper functions for generating invokes.
void InvokePrologue(const ParameterCount& expected,
const ParameterCount& actual,