AuroraMiddleware/v8
1
0
Fork 0
Code Issues 2 Pull Requests Releases Wiki Activity

[wasm-simd][ia32][liftoff] Implement i64x2.abs

Browse Source 
Extract code sequence into macro-assembler for sharing between Liftoff
and TurboFan.

Bug: v8:11416
Change-Id: I8cdce30db8081f6b6c96cca1cbacd035dfc03de4
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2707768
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Reviewed-by: Clemens Backes <clemensb@chromium.org>
Cr-Commit-Position: refs/heads/master@{#72985}
This commit is contained in:
Ng Zhi An 2021-02-23 14:20:33 -08:00 committed by Commit Bot
parent 31aab8384e
commit 0f783b1d8f
4 changed files with 24 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
src/codegen/ia32/macro-assembler-ia32.cc
View File

@ -1053,6 +1053,26 @@ void TurboAssembler::I32x4TruncSatF64x2UZero(XMMRegister dst, XMMRegister src,
}
}
void TurboAssembler::I64x2Abs(XMMRegister dst, XMMRegister src,
XMMRegister scratch) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope avx_scope(this, AVX);
XMMRegister tmp = dst == src ? scratch : dst;
vpxor(tmp, tmp, tmp);
vpsubq(tmp, tmp, src);
vblendvpd(dst, src, tmp, src);
} else {
CpuFeatureScope sse_scope(this, SSE3);
movshdup(scratch, src);
if (dst != src) {
movaps(dst, src);
}
psrad(scratch, 31);
xorps(dst, scratch);
psubq(dst, scratch);
}
}
void TurboAssembler::I64x2GtS(XMMRegister dst, XMMRegister src0,
XMMRegister src1, XMMRegister scratch) {
if (CpuFeatures::IsSupported(AVX)) {

1
src/codegen/ia32/macro-assembler-ia32.h
View File

@ -693,6 +693,7 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
XMMRegister scratch, Register tmp);
void I32x4TruncSatF64x2UZero(XMMRegister dst, XMMRegister src,
XMMRegister scratch, Register tmp);
void I64x2Abs(XMMRegister dst, XMMRegister src, XMMRegister scratch);
void I64x2GtS(XMMRegister dst, XMMRegister src0, XMMRegister src1,
XMMRegister scratch);
void I64x2GeS(XMMRegister dst, XMMRegister src0, XMMRegister src1,

17
src/compiler/backend/ia32/code-generator-ia32.cc
View File

@ -2154,21 +2154,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
case kIA32I64x2Abs: {
XMMRegister dst = i.OutputSimd128Register();
XMMRegister src = i.InputSimd128Register(0);
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope avx_scope(tasm(), AVX);
__ vpxor(dst, dst, dst);
__ vpsubq(dst, dst, src);
__ vblendvpd(dst, src, dst, src);
} else {
CpuFeatureScope sse_scope(tasm(), SSE3);
DCHECK_EQ(dst, src);
__ movshdup(kScratchDoubleReg, src);
__ psrad(kScratchDoubleReg, 31);
__ xorps(dst, kScratchDoubleReg);
__ psubq(dst, kScratchDoubleReg);
}
__ I64x2Abs(i.OutputSimd128Register(), i.InputSimd128Register(0),
kScratchDoubleReg);
break;
}
case kIA32I64x2Neg: {

2
src/wasm/baseline/ia32/liftoff-assembler-ia32.h
View File

@ -4634,7 +4634,7 @@ void LiftoffAssembler::emit_i32x4_abs(LiftoffRegister dst,
void LiftoffAssembler::emit_i64x2_abs(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "i64x2.abs");
I64x2Abs(dst.fp(), src.fp(), liftoff::kScratchDoubleReg);
}
void LiftoffAssembler::emit_i8x16_extract_lane_s(LiftoffRegister dst,