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MIPS[64]: Support for some SIMD operations (5)

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Add support for I32x4Neg, I32x4LtS, I32x4LeS, I32x4LtU, I32x4LeU, I16x8Splat,
I16x8ExtractLane, I16x8ReplaceLane, I16x8Neg, I16x8Shl, I16x8ShrS, I16x8ShrU,
I16x8Add, I16x8AddSaturateS, I16x8Sub, I16x8SubSaturateS for mips32 and mips64
architectures.

BUG=

Review-Url: https://codereview.chromium.org/2795143003
Cr-Commit-Position: refs/heads/master@{#45092}
This commit is contained in:
dusan.simicic 2017-05-04 05:38:18 -07:00 committed by Commit bot
parent 1f2c3596e9
commit 0fad007a98
8 changed files with 426 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

62
src/compiler/instruction-selector.cc
View File

@ -2242,12 +2242,6 @@ void InstructionSelector::VisitI32x4SConvertI16x8High(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI32x4Neg(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4LtS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4LeS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4UConvertI16x8Low(Node* node) {
UNIMPLEMENTED();
}
@ -2256,12 +2250,33 @@ void InstructionSelector::VisitI32x4UConvertI16x8High(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8SConvertI8x16Low(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8SConvertI8x16High(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8SConvertI32x4(Node* node) {
UNIMPLEMENTED();
}
#endif // !V8_TARGET_ARCH_ARM
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
void InstructionSelector::VisitI32x4Neg(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4LtS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4LeS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4LtU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4LeU(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_ARM
#endif // !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
#if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM
#if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS && \
!V8_TARGET_ARCH_MIPS64
void InstructionSelector::VisitI16x8Splat(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8ExtractLane(Node* node) { UNIMPLEMENTED(); }
@ -2272,20 +2287,27 @@ void InstructionSelector::VisitI16x8Shl(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8ShrS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8ShrU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8Add(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8AddSaturateS(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8AddHoriz(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8Sub(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8SubSaturateS(Node* node) {
UNIMPLEMENTED();
}
#endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS &&
// !V8_TARGET_ARCH_MIPS64
#if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM
void InstructionSelector::VisitI16x8AddHoriz(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM
#if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM
void InstructionSelector::VisitI16x8Mul(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8MinS(Node* node) { UNIMPLEMENTED(); }
@ -2296,8 +2318,6 @@ void InstructionSelector::VisitI16x8Eq(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8Ne(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8ShrU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8AddSaturateU(Node* node) {
UNIMPLEMENTED();
}
@ -2311,14 +2331,12 @@ void InstructionSelector::VisitI16x8MinU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8MaxU(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM
#if !V8_TARGET_ARCH_ARM
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
void InstructionSelector::VisitI16x8Neg(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
void InstructionSelector::VisitI16x8SConvertI32x4(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8SConvertI8x16Low(Node* node) {
#if !V8_TARGET_ARCH_ARM
void InstructionSelector::VisitI16x8UConvertI32x4(Node* node) {
UNIMPLEMENTED();
}
@ -2330,18 +2348,10 @@ void InstructionSelector::VisitI16x8UConvertI8x16High(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8SConvertI8x16High(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8LtS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8LeS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8UConvertI32x4(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8LtU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8LeU(Node* node) { UNIMPLEMENTED(); }

101
src/compiler/mips/code-generator-mips.cc
View File

@ -1849,6 +1849,107 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ ftrunc_u_w(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kMipsI32x4Neg: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ subv_w(i.OutputSimd128Register(), kSimd128RegZero,
i.InputSimd128Register(0));
break;
}
case kMipsI32x4LtS: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ clt_s_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMipsI32x4LeS: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ cle_s_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMipsI32x4LtU: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ clt_u_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMipsI32x4LeU: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ cle_u_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMipsI16x8Splat: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ fill_h(i.OutputSimd128Register(), i.InputRegister(0));
break;
}
case kMipsI16x8ExtractLane: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ copy_s_h(i.OutputRegister(), i.InputSimd128Register(0),
i.InputInt8(1));
break;
}
case kMipsI16x8ReplaceLane: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
if (!src.is(dst)) {
__ move_v(dst, src);
}
__ insert_h(dst, i.InputInt8(1), i.InputRegister(2));
break;
}
case kMipsI16x8Neg: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ subv_h(i.OutputSimd128Register(), kSimd128RegZero,
i.InputSimd128Register(0));
break;
}
case kMipsI16x8Shl: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ slli_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputInt4(1));
break;
}
case kMipsI16x8ShrS: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ srai_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputInt4(1));
break;
}
case kMipsI16x8ShrU: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ srli_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputInt4(1));
break;
}
case kMipsI16x8Add: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ addv_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMipsI16x8AddSaturateS: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ adds_s_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMipsI16x8Sub: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ subv_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMipsI16x8SubSaturateS: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ subs_s_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
}
return kSuccess;
} // NOLINT(readability/fn_size)

18
src/compiler/mips/instruction-codes-mips.h
View File

@ -169,7 +169,23 @@ namespace compiler {
V(MipsF32x4Lt) \
V(MipsF32x4Le) \
V(MipsI32x4SConvertF32x4) \
V(MipsI32x4UConvertF32x4)
V(MipsI32x4UConvertF32x4) \
V(MipsI32x4Neg) \
V(MipsI32x4LtS) \
V(MipsI32x4LeS) \
V(MipsI32x4LtU) \
V(MipsI32x4LeU) \
V(MipsI16x8Splat) \
V(MipsI16x8ExtractLane) \
V(MipsI16x8ReplaceLane) \
V(MipsI16x8Neg) \
V(MipsI16x8Shl) \
V(MipsI16x8ShrS) \
V(MipsI16x8ShrU) \
V(MipsI16x8Add) \
V(MipsI16x8AddSaturateS) \
V(MipsI16x8Sub) \
V(MipsI16x8SubSaturateS)
// Addressing modes represent the "shape" of inputs to an instruction.
// Many instructions support multiple addressing modes. Addressing modes

64
src/compiler/mips/instruction-selector-mips.cc
View File

@ -2095,6 +2095,70 @@ void InstructionSelector::VisitI32x4UConvertF32x4(Node* node) {
VisitRR(this, kMipsI32x4UConvertF32x4, node);
}
void InstructionSelector::VisitI32x4Neg(Node* node) {
VisitRR(this, kMipsI32x4Neg, node);
}
void InstructionSelector::VisitI32x4LtS(Node* node) {
VisitRRR(this, kMipsI32x4LtS, node);
}
void InstructionSelector::VisitI32x4LeS(Node* node) {
VisitRRR(this, kMipsI32x4LeS, node);
}
void InstructionSelector::VisitI32x4LtU(Node* node) {
VisitRRR(this, kMipsI32x4LtU, node);
}
void InstructionSelector::VisitI32x4LeU(Node* node) {
VisitRRR(this, kMipsI32x4LeU, node);
}
void InstructionSelector::VisitI16x8Splat(Node* node) {
VisitRR(this, kMipsI16x8Splat, node);
}
void InstructionSelector::VisitI16x8ExtractLane(Node* node) {
VisitRRI(this, kMipsI16x8ExtractLane, node);
}
void InstructionSelector::VisitI16x8ReplaceLane(Node* node) {
VisitRRIR(this, kMipsI16x8ReplaceLane, node);
}
void InstructionSelector::VisitI16x8Neg(Node* node) {
VisitRR(this, kMipsI16x8Neg, node);
}
void InstructionSelector::VisitI16x8Shl(Node* node) {
VisitRRI(this, kMipsI16x8Shl, node);
}
void InstructionSelector::VisitI16x8ShrS(Node* node) {
VisitRRI(this, kMipsI16x8ShrS, node);
}
void InstructionSelector::VisitI16x8ShrU(Node* node) {
VisitRRI(this, kMipsI16x8ShrU, node);
}
void InstructionSelector::VisitI16x8Add(Node* node) {
VisitRRR(this, kMipsI16x8Add, node);
}
void InstructionSelector::VisitI16x8AddSaturateS(Node* node) {
VisitRRR(this, kMipsI16x8AddSaturateS, node);
}
void InstructionSelector::VisitI16x8Sub(Node* node) {
VisitRRR(this, kMipsI16x8Sub, node);
}
void InstructionSelector::VisitI16x8SubSaturateS(Node* node) {
VisitRRR(this, kMipsI16x8SubSaturateS, node);
}
// static
MachineOperatorBuilder::Flags
InstructionSelector::SupportedMachineOperatorFlags() {

101
src/compiler/mips64/code-generator-mips64.cc
View File

@ -2181,6 +2181,107 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ ftrunc_u_w(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kMips64I32x4Neg: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ subv_w(i.OutputSimd128Register(), kSimd128RegZero,
i.InputSimd128Register(0));
break;
}
case kMips64I32x4LtS: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ clt_s_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMips64I32x4LeS: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ cle_s_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMips64I32x4LtU: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ clt_u_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMips64I32x4LeU: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ cle_u_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMips64I16x8Splat: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ fill_h(i.OutputSimd128Register(), i.InputRegister(0));
break;
}
case kMips64I16x8ExtractLane: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ copy_s_h(i.OutputRegister(), i.InputSimd128Register(0),
i.InputInt8(1));
break;
}
case kMips64I16x8ReplaceLane: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
if (!src.is(dst)) {
__ move_v(dst, src);
}
__ insert_h(dst, i.InputInt8(1), i.InputRegister(2));
break;
}
case kMips64I16x8Neg: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ subv_h(i.OutputSimd128Register(), kSimd128RegZero,
i.InputSimd128Register(0));
break;
}
case kMips64I16x8Shl: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ slli_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputInt4(1));
break;
}
case kMips64I16x8ShrS: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ srai_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputInt4(1));
break;
}
case kMips64I16x8ShrU: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ srli_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputInt4(1));
break;
}
case kMips64I16x8Add: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ addv_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMips64I16x8AddSaturateS: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ adds_s_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMips64I16x8Sub: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ subv_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMips64I16x8SubSaturateS: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ subs_s_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
}
return kSuccess;
} // NOLINT(readability/fn_size)

18
src/compiler/mips64/instruction-codes-mips64.h
View File

@ -203,7 +203,23 @@ namespace compiler {
V(Mips64F32x4Lt) \
V(Mips64F32x4Le) \
V(Mips64I32x4SConvertF32x4) \
V(Mips64I32x4UConvertF32x4)
V(Mips64I32x4UConvertF32x4) \
V(Mips64I32x4Neg) \
V(Mips64I32x4LtS) \
V(Mips64I32x4LeS) \
V(Mips64I32x4LtU) \
V(Mips64I32x4LeU) \
V(Mips64I16x8Splat) \
V(Mips64I16x8ExtractLane) \
V(Mips64I16x8ReplaceLane) \
V(Mips64I16x8Neg) \
V(Mips64I16x8Shl) \
V(Mips64I16x8ShrS) \
V(Mips64I16x8ShrU) \
V(Mips64I16x8Add) \
V(Mips64I16x8AddSaturateS) \
V(Mips64I16x8Sub) \
V(Mips64I16x8SubSaturateS)
// Addressing modes represent the "shape" of inputs to an instruction.
// Many instructions support multiple addressing modes. Addressing modes

64
src/compiler/mips64/instruction-selector-mips64.cc
View File

@ -2846,6 +2846,70 @@ void InstructionSelector::VisitI32x4UConvertF32x4(Node* node) {
VisitRR(this, kMips64I32x4UConvertF32x4, node);
}
void InstructionSelector::VisitI32x4Neg(Node* node) {
VisitRR(this, kMips64I32x4Neg, node);
}
void InstructionSelector::VisitI32x4LtS(Node* node) {
VisitRRR(this, kMips64I32x4LtS, node);
}
void InstructionSelector::VisitI32x4LeS(Node* node) {
VisitRRR(this, kMips64I32x4LeS, node);
}
void InstructionSelector::VisitI32x4LtU(Node* node) {
VisitRRR(this, kMips64I32x4LtU, node);
}
void InstructionSelector::VisitI32x4LeU(Node* node) {
VisitRRR(this, kMips64I32x4LeU, node);
}
void InstructionSelector::VisitI16x8Splat(Node* node) {
VisitRR(this, kMips64I16x8Splat, node);
}
void InstructionSelector::VisitI16x8ExtractLane(Node* node) {
VisitRRI(this, kMips64I16x8ExtractLane, node);
}
void InstructionSelector::VisitI16x8ReplaceLane(Node* node) {
VisitRRIR(this, kMips64I16x8ReplaceLane, node);
}
void InstructionSelector::VisitI16x8Neg(Node* node) {
VisitRR(this, kMips64I16x8Neg, node);
}
void InstructionSelector::VisitI16x8Shl(Node* node) {
VisitRRI(this, kMips64I16x8Shl, node);
}
void InstructionSelector::VisitI16x8ShrS(Node* node) {
VisitRRI(this, kMips64I16x8ShrS, node);
}
void InstructionSelector::VisitI16x8ShrU(Node* node) {
VisitRRI(this, kMips64I16x8ShrU, node);
}
void InstructionSelector::VisitI16x8Add(Node* node) {
VisitRRR(this, kMips64I16x8Add, node);
}
void InstructionSelector::VisitI16x8AddSaturateS(Node* node) {
VisitRRR(this, kMips64I16x8AddSaturateS, node);
}
void InstructionSelector::VisitI16x8Sub(Node* node) {
VisitRRR(this, kMips64I16x8Sub, node);
}
void InstructionSelector::VisitI16x8SubSaturateS(Node* node) {
VisitRRR(this, kMips64I16x8SubSaturateS, node);
}
// static
MachineOperatorBuilder::Flags
InstructionSelector::SupportedMachineOperatorFlags() {

34
test/cctest/wasm/test-run-wasm-simd.cc
View File

@ -660,7 +660,8 @@ WASM_EXEC_COMPILED_TEST(I32x4ReplaceLane) {
CHECK_EQ(1, r.Call(1, 2));
}
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64 || SIMD_LOWERING_TARGET
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64 || SIMD_LOWERING_TARGET || \
V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
WASM_EXEC_COMPILED_TEST(I16x8Splat) {
FLAG_wasm_simd_prototype = true;
@ -723,7 +724,8 @@ WASM_EXEC_COMPILED_TEST(I16x8ReplaceLane) {
CHECK_EQ(1, r.Call(1, 2));
}
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64 || SIMD_LOWERING_TARGET
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64 || SIMD_LOWERING_TARGET ||
// V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64
WASM_EXEC_COMPILED_TEST(I8x16Splat) {
@ -942,7 +944,8 @@ WASM_EXEC_COMPILED_TEST(I32x4ConvertI16x8) {
}
#endif // V8_TARGET_ARCH_ARM
#if V8_TARGET_ARCH_ARM || SIMD_LOWERING_TARGET
#if V8_TARGET_ARCH_ARM || SIMD_LOWERING_TARGET || V8_TARGET_ARCH_MIPS || \
V8_TARGET_ARCH_MIPS64
void RunI32x4UnOpTest(WasmOpcode simd_op, Int32UnOp expected_op) {
FLAG_wasm_simd_prototype = true;
WasmRunner<int32_t, int32_t, int32_t> r(kExecuteCompiled);
@ -957,7 +960,10 @@ void RunI32x4UnOpTest(WasmOpcode simd_op, Int32UnOp expected_op) {
}
WASM_EXEC_COMPILED_TEST(I32x4Neg) { RunI32x4UnOpTest(kExprI32x4Neg, Negate); }
#endif // V8_TARGET_ARCH_ARM || SIMD_LOWERING_TARGET || V8_TARGET_ARCH_MIPS ||
// V8_TARGET_ARCH_MIPS64
#if V8_TARGET_ARCH_ARM || SIMD_LOWERING_TARGET
WASM_EXEC_COMPILED_TEST(S128Not) { RunI32x4UnOpTest(kExprS128Not, Not); }
#endif // V8_TARGET_ARCH_ARM || SIMD_LOWERING_TARGET
@ -1045,7 +1051,8 @@ WASM_EXEC_COMPILED_TEST(I32x4Ne) {
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64 || SIMD_LOWERING_TARGET ||
// V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
#if V8_TARGET_ARCH_ARM || SIMD_LOWERING_TARGET
#if V8_TARGET_ARCH_ARM || SIMD_LOWERING_TARGET || V8_TARGET_ARCH_MIPS || \
V8_TARGET_ARCH_MIPS64
WASM_EXEC_COMPILED_TEST(I32x4LtS) {
RunI32x4CompareOpTest(kExprI32x4LtS, Less);
}
@ -1077,7 +1084,8 @@ WASM_EXEC_COMPILED_TEST(I32x4GtU) {
WASM_EXEC_COMPILED_TEST(I32x4GeU) {
RunI32x4CompareOpTest(kExprI32x4GeU, UnsignedGreaterEqual);
}
#endif // V8_TARGET_ARCH_ARM || SIMD_LOWERING_TARGET
#endif // V8_TARGET_ARCH_ARM || SIMD_LOWERING_TARGET || V8_TARGET_ARCH_MIPS ||
// V8_TARGET_ARCH_MIPS64
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64 || SIMD_LOWERING_TARGET || \
V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
@ -1135,7 +1143,9 @@ WASM_EXEC_COMPILED_TEST(I16x8ConvertI8x16) {
CHECK_EQ(1, r.Call(*i, unpacked_signed, unpacked_unsigned));
}
}
#endif // V8_TARGET_ARCH_ARM
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
void RunI16x8UnOpTest(WasmOpcode simd_op, Int16UnOp expected_op) {
FLAG_wasm_simd_prototype = true;
WasmRunner<int32_t, int32_t, int32_t> r(kExecuteCompiled);
@ -1150,7 +1160,9 @@ void RunI16x8UnOpTest(WasmOpcode simd_op, Int16UnOp expected_op) {
}
WASM_EXEC_COMPILED_TEST(I16x8Neg) { RunI16x8UnOpTest(kExprI16x8Neg, Negate); }
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
#if V8_TARGET_ARCH_ARM
// Tests both signed and unsigned conversion from I32x4 (packing).
WASM_EXEC_COMPILED_TEST(I16x8ConvertI32x4) {
FLAG_wasm_simd_prototype = true;
@ -1181,7 +1193,8 @@ WASM_EXEC_COMPILED_TEST(I16x8ConvertI32x4) {
}
#endif // V8_TARGET_ARCH_ARM
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64 || SIMD_LOWERING_TARGET
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64 || SIMD_LOWERING_TARGET || \
V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
void RunI16x8BinOpTest(WasmOpcode simd_op, Int16BinOp expected_op) {
FLAG_wasm_simd_prototype = true;
WasmRunner<int32_t, int32_t, int32_t, int32_t> r(kExecuteCompiled);
@ -1212,7 +1225,10 @@ WASM_EXEC_COMPILED_TEST(I16x8Sub) { RunI16x8BinOpTest(kExprI16x8Sub, Sub); }
WASM_EXEC_COMPILED_TEST(I16x8SubSaturateS) {
RunI16x8BinOpTest(kExprI16x8SubSaturateS, SubSaturate);
}
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64 || SIMD_LOWERING_TARGET ||
// V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64 || SIMD_LOWERING_TARGET
WASM_EXEC_COMPILED_TEST(I16x8Mul) { RunI16x8BinOpTest(kExprI16x8Mul, Mul); }
WASM_EXEC_COMPILED_TEST(I16x8MinS) {
@ -1301,7 +1317,8 @@ WASM_EXEC_COMPILED_TEST(I16x8LeU) {
}
#endif // V8_TARGET_ARCH_ARM || SIMD_LOWERING_TARGET
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64 || SIMD_LOWERING_TARGET
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64 || SIMD_LOWERING_TARGET || \
V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
void RunI16x8ShiftOpTest(WasmOpcode simd_op, Int16ShiftOp expected_op,
int shift) {
FLAG_wasm_simd_prototype = true;
@ -1328,7 +1345,8 @@ WASM_EXEC_COMPILED_TEST(I16x8ShrS) {
WASM_EXEC_COMPILED_TEST(I16x8ShrU) {
RunI16x8ShiftOpTest(kExprI16x8ShrU, LogicalShiftRight, 1);
}
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64 || SIMD_LOWERING_TARGET
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64 || SIMD_LOWERING_TARGET ||
// V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
#if V8_TARGET_ARCH_ARM
void RunI8x16UnOpTest(WasmOpcode simd_op, Int8UnOp expected_op) {