diff --git a/src/mips/simulator-mips.cc b/src/mips/simulator-mips.cc
index bd423996d8..7ff3d144e7 100644
--- a/src/mips/simulator-mips.cc
+++ b/src/mips/simulator-mips.cc
@@ -2537,11 +2537,11 @@ void Simulator::DecodeTypeRegisterDRsType() {
       break;
     case MADDF_D:
       DCHECK(IsMipsArchVariant(kMips32r6));
-      set_fpu_register_double(fd_reg(), fd + (fs * ft));
+      set_fpu_register_double(fd_reg(), std::fma(fs, ft, fd));
       break;
     case MSUBF_D:
       DCHECK(IsMipsArchVariant(kMips32r6));
-      set_fpu_register_double(fd_reg(), fd - (fs * ft));
+      set_fpu_register_double(fd_reg(), std::fma(-fs, ft, fd));
       break;
     case MUL_D:
       set_fpu_register_double(
@@ -2964,11 +2964,11 @@ void Simulator::DecodeTypeRegisterSRsType() {
       break;
     case MADDF_S:
       DCHECK(IsMipsArchVariant(kMips32r6));
-      set_fpu_register_float(fd_reg(), fd + (fs * ft));
+      set_fpu_register_float(fd_reg(), std::fma(fs, ft, fd));
       break;
     case MSUBF_S:
       DCHECK(IsMipsArchVariant(kMips32r6));
-      set_fpu_register_float(fd_reg(), fd - (fs * ft));
+      set_fpu_register_float(fd_reg(), std::fma(-fs, ft, fd));
       break;
     case MUL_S:
       set_fpu_register_float(
diff --git a/src/mips64/simulator-mips64.cc b/src/mips64/simulator-mips64.cc
index 4a8e0076d9..591ddaf3a1 100644
--- a/src/mips64/simulator-mips64.cc
+++ b/src/mips64/simulator-mips64.cc
@@ -2475,11 +2475,11 @@ void Simulator::DecodeTypeRegisterSRsType() {
       break;
     case MADDF_S:
       DCHECK(kArchVariant == kMips64r6);
-      set_fpu_register_float(fd_reg(), fd + (fs * ft));
+      set_fpu_register_float(fd_reg(), std::fma(fs, ft, fd));
       break;
     case MSUBF_S:
       DCHECK(kArchVariant == kMips64r6);
-      set_fpu_register_float(fd_reg(), fd - (fs * ft));
+      set_fpu_register_float(fd_reg(), std::fma(-fs, ft, fd));
       break;
     case MUL_S:
       set_fpu_register_float(
@@ -2901,11 +2901,11 @@ void Simulator::DecodeTypeRegisterDRsType() {
       break;
     case MADDF_D:
       DCHECK(kArchVariant == kMips64r6);
-      set_fpu_register_double(fd_reg(), fd + (fs * ft));
+      set_fpu_register_double(fd_reg(), std::fma(fs, ft, fd));
       break;
     case MSUBF_D:
       DCHECK(kArchVariant == kMips64r6);
-      set_fpu_register_double(fd_reg(), fd - (fs * ft));
+      set_fpu_register_double(fd_reg(), std::fma(-fs, ft, fd));
       break;
     case MUL_D:
       set_fpu_register_double(
diff --git a/test/cctest/test-assembler-mips.cc b/test/cctest/test-assembler-mips.cc
index 08d3c606c0..191589a73a 100644
--- a/test/cctest/test-assembler-mips.cc
+++ b/test/cctest/test-assembler-mips.cc
@@ -5457,12 +5457,14 @@ void helper_madd_msub_maddf_msubf(F func) {
 
     (CALL_GENERATED_CODE(isolate, f, &tc, 0, 0, 0, 0));
 
-    T res_add = tc.fr + (tc.fs * tc.ft);
+    T res_add = 0;
     T res_sub = 0;
     if (IsMipsArchVariant(kMips32r2)) {
+      res_add = (tc.fs * tc.ft) + tc.fr;
       res_sub = (tc.fs * tc.ft) - tc.fr;
     } else if (IsMipsArchVariant(kMips32r6)) {
-      res_sub = tc.fr - (tc.fs * tc.ft);
+      res_add = std::fma(tc.fs, tc.ft, tc.fr);
+      res_sub = std::fma(-tc.fs, tc.ft, tc.fr);
     } else {
       UNREACHABLE();
     }
diff --git a/test/cctest/test-assembler-mips64.cc b/test/cctest/test-assembler-mips64.cc
index b0315343b5..0ec51723e9 100644
--- a/test/cctest/test-assembler-mips64.cc
+++ b/test/cctest/test-assembler-mips64.cc
@@ -6005,12 +6005,14 @@ void helper_madd_msub_maddf_msubf(F func) {
 
     (CALL_GENERATED_CODE(isolate, f, &tc, 0, 0, 0, 0));
 
-    T res_add = tc.fr + (tc.fs * tc.ft);
     T res_sub;
+    T res_add;
     if (kArchVariant != kMips64r6) {
+      res_add = tc.fr + (tc.fs * tc.ft);
       res_sub = (tc.fs * tc.ft) - tc.fr;
     } else {
-      res_sub = tc.fr - (tc.fs * tc.ft);
+      res_add = std::fma(tc.fs, tc.ft, tc.fr);
+      res_sub = std::fma(-tc.fs, tc.ft, tc.fr);
     }
 
     CHECK_EQ(tc.fd_add, res_add);