ppc: [liftoff] implement fp copysign
Change-Id: Ic1fb152ced8535982f4e918df691e5c6e4cfaa68 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3063506 Reviewed-by: Milad Fa <mfarazma@redhat.com> Commit-Queue: Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/master@{#76025}
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@ -1620,6 +1620,12 @@ void Assembler::fmul(const DoubleRegister frt, const DoubleRegister fra,
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rc);
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rc);
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}
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}
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void Assembler::fcpsgn(const DoubleRegister frt, const DoubleRegister fra,
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const DoubleRegister frc, RCBit rc) {
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emit(EXT4 | FCPSGN | frt.code() * B21 | fra.code() * B16 | frc.code() * B6 |
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rc);
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}
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void Assembler::fdiv(const DoubleRegister frt, const DoubleRegister fra,
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void Assembler::fdiv(const DoubleRegister frt, const DoubleRegister fra,
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const DoubleRegister frb, RCBit rc) {
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const DoubleRegister frb, RCBit rc) {
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a_form(EXT4 | FDIV, frt, fra, frb, rc);
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a_form(EXT4 | FDIV, frt, fra, frb, rc);
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@ -1055,6 +1055,8 @@ class Assembler : public AssemblerBase {
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void fmsub(const DoubleRegister frt, const DoubleRegister fra,
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void fmsub(const DoubleRegister frt, const DoubleRegister fra,
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const DoubleRegister frc, const DoubleRegister frb,
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const DoubleRegister frc, const DoubleRegister frb,
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RCBit rc = LeaveRC);
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RCBit rc = LeaveRC);
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void fcpsgn(const DoubleRegister frt, const DoubleRegister fra,
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const DoubleRegister frc, RCBit rc = LeaveRC);
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// Vector instructions
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// Vector instructions
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void mfvsrd(const Register ra, const Simd128Register r);
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void mfvsrd(const Register ra, const Simd128Register r);
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@ -1302,6 +1302,10 @@ void Decoder::DecodeExt4(Instruction* instr) {
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Format(instr, "fneg'. 'Dt, 'Db");
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Format(instr, "fneg'. 'Dt, 'Db");
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break;
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break;
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}
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}
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case FCPSGN: {
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Format(instr, "fcpsgn'. 'Dt, 'Da, 'Db");
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break;
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}
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case MCRFS: {
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case MCRFS: {
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Format(instr, "mcrfs ?,?");
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Format(instr, "mcrfs ?,?");
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break;
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break;
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@ -3677,6 +3677,16 @@ void Simulator::ExecuteGeneric(Instruction* instr) {
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set_d_register_from_double(frt, frt_val);
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set_d_register_from_double(frt, frt_val);
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return;
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return;
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}
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}
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case FCPSGN: {
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int frt = instr->RTValue();
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int frb = instr->RBValue();
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int fra = instr->RAValue();
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double frb_val = get_double_from_d_register(frb);
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double fra_val = get_double_from_d_register(fra);
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double frt_val = std::copysign(fra_val, frb_val);
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set_d_register_from_double(frt, frt_val);
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return;
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}
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case FMR: {
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case FMR: {
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int frt = instr->RTValue();
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int frt = instr->RTValue();
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int frb = instr->RBValue();
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int frb = instr->RBValue();
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@ -784,9 +784,6 @@ void LiftoffAssembler::FillStackSlotsWithZero(int start, int size) {
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bailout(kUnsupportedArchitecture, "i64 shiftop: " #name); \
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bailout(kUnsupportedArchitecture, "i64 shiftop: " #name); \
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}
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}
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UNIMPLEMENTED_FP_BINOP(f32_copysign)
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UNIMPLEMENTED_FP_BINOP(f64_copysign)
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#undef UNIMPLEMENTED_I32_BINOP
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#undef UNIMPLEMENTED_I32_BINOP
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#undef UNIMPLEMENTED_I32_BINOP_I
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#undef UNIMPLEMENTED_I32_BINOP_I
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#undef UNIMPLEMENTED_I64_BINOP
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#undef UNIMPLEMENTED_I64_BINOP
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@ -868,6 +865,10 @@ UNOP_LIST(EMIT_UNOP_FUNCTION)
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// V(name, instr, dtype, stype1, stype2, dcast, scast1, scast2, rcast,
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// V(name, instr, dtype, stype1, stype2, dcast, scast1, scast2, rcast,
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// return_val, return_type)
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// return_val, return_type)
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#define BINOP_LIST(V) \
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#define BINOP_LIST(V) \
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V(f32_copysign, fcpsgn, DoubleRegister, DoubleRegister, DoubleRegister, , , \
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, ROUND_F64_TO_F32, , void) \
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V(f64_copysign, fcpsgn, DoubleRegister, DoubleRegister, DoubleRegister, , , \
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, USE, , void) \
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V(f32_min, MinF64, DoubleRegister, DoubleRegister, DoubleRegister, , , , \
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V(f32_min, MinF64, DoubleRegister, DoubleRegister, DoubleRegister, , , , \
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USE, , void) \
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USE, , void) \
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V(f32_max, MaxF64, DoubleRegister, DoubleRegister, DoubleRegister, , , , \
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V(f32_max, MaxF64, DoubleRegister, DoubleRegister, DoubleRegister, , , , \
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