From 12ac48d2727fa4d1cc343d5535cbc017b87ecb36 Mon Sep 17 00:00:00 2001 From: Milad Farazmand Date: Thu, 7 May 2020 18:07:50 +0000 Subject: [PATCH] PPC: [wasm-simd] Implement simd ExtractLane Change-Id: Ic71dda9c487b6afa95ba2525518c923f2608fd7d Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2187003 Reviewed-by: Junliang Yan Commit-Queue: Milad Farazmand Cr-Commit-Position: refs/heads/master@{#67661} --- src/codegen/ppc/assembler-ppc.cc | 10 +++++ src/codegen/ppc/assembler-ppc.h | 2 + .../backend/ppc/code-generator-ppc.cc | 40 +++++++++++++++++++ .../backend/ppc/instruction-codes-ppc.h | 8 ++++ .../backend/ppc/instruction-scheduler-ppc.cc | 8 ++++ .../backend/ppc/instruction-selector-ppc.cc | 5 ++- 6 files changed, 72 insertions(+), 1 deletion(-) diff --git a/src/codegen/ppc/assembler-ppc.cc b/src/codegen/ppc/assembler-ppc.cc index 095a9f18ff..b9f09e23f2 100644 --- a/src/codegen/ppc/assembler-ppc.cc +++ b/src/codegen/ppc/assembler-ppc.cc @@ -1758,6 +1758,16 @@ void Assembler::fmsub(const DoubleRegister frt, const DoubleRegister fra, } // Vector instructions +void Assembler::mfvsrd(const Register ra, const DoubleRegister rs) { + int SX = 1; + emit(MFVSRD | rs.code() * B21 | ra.code() * B16 | SX); +} + +void Assembler::mfvsrwz(const Register ra, const DoubleRegister rs) { + int SX = 1; + emit(MFVSRWZ | rs.code() * B21 | ra.code() * B16 | SX); +} + void Assembler::mtvsrd(const DoubleRegister rt, const Register ra) { int TX = 1; emit(MTVSRD | rt.code() * B21 | ra.code() * B16 | TX); diff --git a/src/codegen/ppc/assembler-ppc.h b/src/codegen/ppc/assembler-ppc.h index 9125ffb63e..778e94c185 100644 --- a/src/codegen/ppc/assembler-ppc.h +++ b/src/codegen/ppc/assembler-ppc.h @@ -947,6 +947,8 @@ class Assembler : public AssemblerBase { RCBit rc = LeaveRC); // Vector instructions + void mfvsrd(const Register ra, const DoubleRegister r); + void mfvsrwz(const Register ra, const DoubleRegister r); void mtvsrd(const DoubleRegister rt, const Register ra); void vor(const DoubleRegister rt, const DoubleRegister ra, const DoubleRegister rb); diff --git a/src/compiler/backend/ppc/code-generator-ppc.cc b/src/compiler/backend/ppc/code-generator-ppc.cc index 1a19882ab5..d9b17c826a 100644 --- a/src/compiler/backend/ppc/code-generator-ppc.cc +++ b/src/compiler/backend/ppc/code-generator-ppc.cc @@ -2208,6 +2208,46 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( __ vspltb(dst, dst, Operand(7)); break; } + case kPPC_F64x2ExtractLane: { + __ mfvsrd(kScratchReg, i.InputSimd128Register(0)); + __ MovInt64ToDouble(i.OutputDoubleRegister(), kScratchReg); + break; + } + case kPPC_F32x4ExtractLane: { + __ mfvsrwz(kScratchReg, i.InputSimd128Register(0)); + __ MovIntToFloat(i.OutputDoubleRegister(), kScratchReg); + break; + } + case kPPC_I64x2ExtractLane: { + __ mfvsrd(i.OutputRegister(), i.InputSimd128Register(0)); + break; + } + case kPPC_I32x4ExtractLane: { + __ mfvsrwz(i.OutputRegister(), i.InputSimd128Register(0)); + break; + } + case kPPC_I16x8ExtractLaneU: { + __ mfvsrwz(r0, i.InputSimd128Register(0)); + __ li(ip, Operand(16)); + __ srd(i.OutputRegister(), r0, ip); + break; + } + case kPPC_I16x8ExtractLaneS: { + __ mfvsrwz(kScratchReg, i.InputSimd128Register(0)); + __ sradi(i.OutputRegister(), kScratchReg, 16); + break; + } + case kPPC_I8x16ExtractLaneU: { + __ mfvsrwz(r0, i.InputSimd128Register(0)); + __ li(ip, Operand(24)); + __ srd(i.OutputRegister(), r0, ip); + break; + } + case kPPC_I8x16ExtractLaneS: { + __ mfvsrwz(kScratchReg, i.InputSimd128Register(0)); + __ sradi(i.OutputRegister(), kScratchReg, 24); + break; + } case kPPC_StoreCompressTagged: { ASSEMBLE_STORE_INTEGER(StoreTaggedField, StoreTaggedFieldX); break; diff --git a/src/compiler/backend/ppc/instruction-codes-ppc.h b/src/compiler/backend/ppc/instruction-codes-ppc.h index 1d80eeb738..4f6aeced6d 100644 --- a/src/compiler/backend/ppc/instruction-codes-ppc.h +++ b/src/compiler/backend/ppc/instruction-codes-ppc.h @@ -191,11 +191,19 @@ namespace compiler { V(PPC_AtomicXorInt32) \ V(PPC_AtomicXorInt64) \ V(PPC_F64x2Splat) \ + V(PPC_F64x2ExtractLane) \ V(PPC_F32x4Splat) \ + V(PPC_F32x4ExtractLane) \ V(PPC_I64x2Splat) \ + V(PPC_I64x2ExtractLane) \ V(PPC_I32x4Splat) \ + V(PPC_I32x4ExtractLane) \ V(PPC_I16x8Splat) \ + V(PPC_I16x8ExtractLaneU) \ + V(PPC_I16x8ExtractLaneS) \ V(PPC_I8x16Splat) \ + V(PPC_I8x16ExtractLaneU) \ + V(PPC_I8x16ExtractLaneS) \ V(PPC_StoreCompressTagged) \ V(PPC_LoadDecompressTaggedSigned) \ V(PPC_LoadDecompressTaggedPointer) \ diff --git a/src/compiler/backend/ppc/instruction-scheduler-ppc.cc b/src/compiler/backend/ppc/instruction-scheduler-ppc.cc index 252d30a785..68d0aaedc4 100644 --- a/src/compiler/backend/ppc/instruction-scheduler-ppc.cc +++ b/src/compiler/backend/ppc/instruction-scheduler-ppc.cc @@ -114,11 +114,19 @@ int InstructionScheduler::GetTargetInstructionFlags( case kPPC_CompressPointer: case kPPC_CompressAny: case kPPC_F64x2Splat: + case kPPC_F64x2ExtractLane: case kPPC_F32x4Splat: + case kPPC_F32x4ExtractLane: case kPPC_I64x2Splat: + case kPPC_I64x2ExtractLane: case kPPC_I32x4Splat: + case kPPC_I32x4ExtractLane: case kPPC_I16x8Splat: + case kPPC_I16x8ExtractLaneU: + case kPPC_I16x8ExtractLaneS: case kPPC_I8x16Splat: + case kPPC_I8x16ExtractLaneU: + case kPPC_I8x16ExtractLaneS: return kNoOpcodeFlags; case kPPC_LoadWordS8: diff --git a/src/compiler/backend/ppc/instruction-selector-ppc.cc b/src/compiler/backend/ppc/instruction-selector-ppc.cc index 877601bcd5..1598fbad04 100644 --- a/src/compiler/backend/ppc/instruction-selector-ppc.cc +++ b/src/compiler/backend/ppc/instruction-selector-ppc.cc @@ -2139,7 +2139,10 @@ SIMD_TYPES(SIMD_VISIT_SPLAT) #define SIMD_VISIT_EXTRACT_LANE(Type, Sign) \ void InstructionSelector::Visit##Type##ExtractLane##Sign(Node* node) { \ - UNIMPLEMENTED(); \ + PPCOperandGenerator g(this); \ + int32_t lane = OpParameter(node->op()); \ + Emit(kPPC_##Type##ExtractLane##Sign, g.DefineAsRegister(node), \ + g.UseRegister(node->InputAt(0)), g.UseImmediate(lane)); \ } SIMD_VISIT_EXTRACT_LANE(F64x2, ) SIMD_VISIT_EXTRACT_LANE(F32x4, )