S390 [liftoff]: Implement simd f32x2 unops
Implementations are added to macro-assembler to be shared between liftoff and code generator. Change-Id: I945e312b45d87e021ffd64948bdfd69d0642fb83 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3387608 Reviewed-by: Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Farazmand <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/main@{#78630}
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@ -5235,7 +5235,14 @@ void TurboAssembler::I8x16ReplaceLane(Simd128Register dst, Simd128Register src1,
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V(F64x2Ceil, vfi, 6, 0, 3) \
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V(F64x2Ceil, vfi, 6, 0, 3) \
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V(F64x2Floor, vfi, 7, 0, 3) \
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V(F64x2Floor, vfi, 7, 0, 3) \
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V(F64x2Trunc, vfi, 5, 0, 3) \
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V(F64x2Trunc, vfi, 5, 0, 3) \
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V(F64x2NearestInt, vfi, 4, 0, 3)
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V(F64x2NearestInt, vfi, 4, 0, 3) \
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V(F32x4Abs, vfpso, 2, 0, 2) \
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V(F32x4Neg, vfpso, 0, 0, 2) \
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V(F32x4Sqrt, vfsq, 0, 0, 2) \
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V(F32x4Ceil, vfi, 6, 0, 2) \
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V(F32x4Floor, vfi, 7, 0, 2) \
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V(F32x4Trunc, vfi, 5, 0, 2) \
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V(F32x4NearestInt, vfi, 4, 0, 2)
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#define EMIT_SIMD_UNOP_VRR_A(name, op, c1, c2, c3) \
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#define EMIT_SIMD_UNOP_VRR_A(name, op, c1, c2, c3) \
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void TurboAssembler::name(Simd128Register dst, Simd128Register src) { \
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void TurboAssembler::name(Simd128Register dst, Simd128Register src) { \
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@ -1113,7 +1113,14 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
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V(F64x2Ceil) \
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V(F64x2Ceil) \
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V(F64x2Floor) \
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V(F64x2Floor) \
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V(F64x2Trunc) \
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V(F64x2Trunc) \
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V(F64x2NearestInt)
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V(F64x2NearestInt) \
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V(F32x4Abs) \
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V(F32x4Neg) \
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V(F32x4Sqrt) \
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V(F32x4Ceil) \
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V(F32x4Floor) \
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V(F32x4Trunc) \
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V(F32x4NearestInt)
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#define PROTOTYPE_SIMD_UNOP(name) \
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#define PROTOTYPE_SIMD_UNOP(name) \
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void name(Simd128Register dst, Simd128Register src);
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void name(Simd128Register dst, Simd128Register src);
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@ -2656,7 +2656,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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V(F64x2Ceil, Simd128Register, Simd128Register) \
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V(F64x2Ceil, Simd128Register, Simd128Register) \
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V(F64x2Floor, Simd128Register, Simd128Register) \
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V(F64x2Floor, Simd128Register, Simd128Register) \
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V(F64x2Trunc, Simd128Register, Simd128Register) \
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V(F64x2Trunc, Simd128Register, Simd128Register) \
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V(F64x2NearestInt, Simd128Register, Simd128Register)
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V(F64x2NearestInt, Simd128Register, Simd128Register) \
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V(F32x4Abs, Simd128Register, Simd128Register) \
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V(F32x4Neg, Simd128Register, Simd128Register) \
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V(F32x4Sqrt, Simd128Register, Simd128Register) \
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V(F32x4Ceil, Simd128Register, Simd128Register) \
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V(F32x4Floor, Simd128Register, Simd128Register) \
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V(F32x4Trunc, Simd128Register, Simd128Register) \
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V(F32x4NearestInt, Simd128Register, Simd128Register)
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#define EMIT_SIMD_UNOP(name, dtype, stype) \
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#define EMIT_SIMD_UNOP(name, dtype, stype) \
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case kS390_##name: { \
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case kS390_##name: { \
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@ -2749,16 +2756,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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break;
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break;
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}
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}
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// vector unary ops
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// vector unary ops
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case kS390_F32x4Abs: {
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__ vfpso(i.OutputSimd128Register(), i.InputSimd128Register(0),
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Condition(2), Condition(0), Condition(2));
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break;
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}
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case kS390_F32x4Neg: {
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__ vfpso(i.OutputSimd128Register(), i.InputSimd128Register(0),
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Condition(0), Condition(0), Condition(2));
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break;
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}
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case kS390_I64x2Neg: {
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case kS390_I64x2Neg: {
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__ vlc(i.OutputSimd128Register(), i.InputSimd128Register(0), Condition(0),
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__ vlc(i.OutputSimd128Register(), i.InputSimd128Register(0), Condition(0),
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Condition(0), Condition(3));
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Condition(0), Condition(3));
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@ -2799,11 +2796,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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Condition(2));
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Condition(2));
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break;
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break;
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}
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}
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case kS390_F32x4Sqrt: {
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__ vfsq(i.OutputSimd128Register(), i.InputSimd128Register(0),
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Condition(0), Condition(0), Condition(2));
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break;
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}
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case kS390_S128Not: {
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case kS390_S128Not: {
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Simd128Register src = i.InputSimd128Register(0);
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Simd128Register src = i.InputSimd128Register(0);
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Simd128Register dst = i.OutputSimd128Register();
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Simd128Register dst = i.OutputSimd128Register();
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@ -3266,26 +3258,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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Condition(3));
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Condition(3));
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break;
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break;
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}
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}
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case kS390_F32x4Ceil: {
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__ vfi(i.OutputSimd128Register(), i.InputSimd128Register(0), Condition(6),
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Condition(0), Condition(2));
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break;
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}
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case kS390_F32x4Floor: {
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__ vfi(i.OutputSimd128Register(), i.InputSimd128Register(0), Condition(7),
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Condition(0), Condition(2));
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break;
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}
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case kS390_F32x4Trunc: {
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__ vfi(i.OutputSimd128Register(), i.InputSimd128Register(0), Condition(5),
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Condition(0), Condition(2));
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break;
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}
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case kS390_F32x4NearestInt: {
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__ vfi(i.OutputSimd128Register(), i.InputSimd128Register(0), Condition(4),
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Condition(0), Condition(2));
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break;
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}
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case kS390_I32x4DotI16x8S: {
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case kS390_I32x4DotI16x8S: {
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Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
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Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
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__ vme(kScratchDoubleReg, i.InputSimd128Register(0),
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__ vme(kScratchDoubleReg, i.InputSimd128Register(0),
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@ -2389,7 +2389,14 @@ SIMD_BINOP_RI_LIST(EMIT_SIMD_BINOP_RI)
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V(f64x2_ceil, F64x2Ceil, fp, fp, true, bool) \
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V(f64x2_ceil, F64x2Ceil, fp, fp, true, bool) \
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V(f64x2_floor, F64x2Floor, fp, fp, true, bool) \
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V(f64x2_floor, F64x2Floor, fp, fp, true, bool) \
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V(f64x2_trunc, F64x2Trunc, fp, fp, true, bool) \
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V(f64x2_trunc, F64x2Trunc, fp, fp, true, bool) \
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V(f64x2_nearest_int, F64x2NearestInt, fp, fp, true, bool)
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V(f64x2_nearest_int, F64x2NearestInt, fp, fp, true, bool) \
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V(f32x4_abs, F32x4Abs, fp, fp, , void) \
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V(f32x4_neg, F32x4Neg, fp, fp, , void) \
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V(f32x4_sqrt, F32x4Sqrt, fp, fp, , void) \
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V(f32x4_ceil, F32x4Ceil, fp, fp, true, bool) \
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V(f32x4_floor, F32x4Floor, fp, fp, true, bool) \
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V(f32x4_trunc, F32x4Trunc, fp, fp, true, bool) \
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V(f32x4_nearest_int, F32x4NearestInt, fp, fp, true, bool)
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#define EMIT_SIMD_UNOP(name, op, dtype, stype, return_val, return_type) \
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#define EMIT_SIMD_UNOP(name, op, dtype, stype, return_val, return_type) \
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return_type LiftoffAssembler::emit_##name(LiftoffRegister dst, \
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return_type LiftoffAssembler::emit_##name(LiftoffRegister dst, \
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@ -2491,45 +2498,6 @@ void LiftoffAssembler::emit_f64x2_promote_low_f32x4(LiftoffRegister dst,
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bailout(kSimd, "f64x2.promote_low_f32x4");
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bailout(kSimd, "f64x2.promote_low_f32x4");
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}
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}
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void LiftoffAssembler::emit_f32x4_abs(LiftoffRegister dst,
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LiftoffRegister src) {
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bailout(kUnsupportedArchitecture, "emit_f32x4_abs");
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}
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void LiftoffAssembler::emit_f32x4_neg(LiftoffRegister dst,
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LiftoffRegister src) {
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bailout(kUnsupportedArchitecture, "emit_f32x4neg");
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}
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void LiftoffAssembler::emit_f32x4_sqrt(LiftoffRegister dst,
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LiftoffRegister src) {
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bailout(kUnsupportedArchitecture, "emit_f32x4sqrt");
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}
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bool LiftoffAssembler::emit_f32x4_ceil(LiftoffRegister dst,
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LiftoffRegister src) {
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bailout(kSimd, "f32x4.ceil");
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return true;
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}
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bool LiftoffAssembler::emit_f32x4_floor(LiftoffRegister dst,
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LiftoffRegister src) {
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bailout(kSimd, "f32x4.floor");
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return true;
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}
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bool LiftoffAssembler::emit_f32x4_trunc(LiftoffRegister dst,
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LiftoffRegister src) {
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bailout(kSimd, "f32x4.trunc");
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return true;
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}
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bool LiftoffAssembler::emit_f32x4_nearest_int(LiftoffRegister dst,
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LiftoffRegister src) {
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bailout(kSimd, "f32x4.nearest_int");
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return true;
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}
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void LiftoffAssembler::emit_f32x4_pmin(LiftoffRegister dst, LiftoffRegister lhs,
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void LiftoffAssembler::emit_f32x4_pmin(LiftoffRegister dst, LiftoffRegister lhs,
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LiftoffRegister rhs) {
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LiftoffRegister rhs) {
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bailout(kSimd, "pmin unimplemented");
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bailout(kSimd, "pmin unimplemented");
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