S390 [liftoff]: Implement simd f32x2 unops

Implementations are added to macro-assembler to be shared between
liftoff and code generator.

Change-Id: I945e312b45d87e021ffd64948bdfd69d0642fb83
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3387608
Reviewed-by: Junliang Yan <junyan@redhat.com>
Commit-Queue: Milad Farazmand <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/main@{#78630}
This commit is contained in:
Milad Fa 2022-01-13 12:40:58 -05:00 committed by V8 LUCI CQ
parent 2e147b4fae
commit 12b7c45259
4 changed files with 65 additions and 111 deletions

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@ -5235,7 +5235,14 @@ void TurboAssembler::I8x16ReplaceLane(Simd128Register dst, Simd128Register src1,
V(F64x2Ceil, vfi, 6, 0, 3) \ V(F64x2Ceil, vfi, 6, 0, 3) \
V(F64x2Floor, vfi, 7, 0, 3) \ V(F64x2Floor, vfi, 7, 0, 3) \
V(F64x2Trunc, vfi, 5, 0, 3) \ V(F64x2Trunc, vfi, 5, 0, 3) \
V(F64x2NearestInt, vfi, 4, 0, 3) V(F64x2NearestInt, vfi, 4, 0, 3) \
V(F32x4Abs, vfpso, 2, 0, 2) \
V(F32x4Neg, vfpso, 0, 0, 2) \
V(F32x4Sqrt, vfsq, 0, 0, 2) \
V(F32x4Ceil, vfi, 6, 0, 2) \
V(F32x4Floor, vfi, 7, 0, 2) \
V(F32x4Trunc, vfi, 5, 0, 2) \
V(F32x4NearestInt, vfi, 4, 0, 2)
#define EMIT_SIMD_UNOP_VRR_A(name, op, c1, c2, c3) \ #define EMIT_SIMD_UNOP_VRR_A(name, op, c1, c2, c3) \
void TurboAssembler::name(Simd128Register dst, Simd128Register src) { \ void TurboAssembler::name(Simd128Register dst, Simd128Register src) { \

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@ -1113,7 +1113,14 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
V(F64x2Ceil) \ V(F64x2Ceil) \
V(F64x2Floor) \ V(F64x2Floor) \
V(F64x2Trunc) \ V(F64x2Trunc) \
V(F64x2NearestInt) V(F64x2NearestInt) \
V(F32x4Abs) \
V(F32x4Neg) \
V(F32x4Sqrt) \
V(F32x4Ceil) \
V(F32x4Floor) \
V(F32x4Trunc) \
V(F32x4NearestInt)
#define PROTOTYPE_SIMD_UNOP(name) \ #define PROTOTYPE_SIMD_UNOP(name) \
void name(Simd128Register dst, Simd128Register src); void name(Simd128Register dst, Simd128Register src);

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@ -2656,7 +2656,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
V(F64x2Ceil, Simd128Register, Simd128Register) \ V(F64x2Ceil, Simd128Register, Simd128Register) \
V(F64x2Floor, Simd128Register, Simd128Register) \ V(F64x2Floor, Simd128Register, Simd128Register) \
V(F64x2Trunc, Simd128Register, Simd128Register) \ V(F64x2Trunc, Simd128Register, Simd128Register) \
V(F64x2NearestInt, Simd128Register, Simd128Register) V(F64x2NearestInt, Simd128Register, Simd128Register) \
V(F32x4Abs, Simd128Register, Simd128Register) \
V(F32x4Neg, Simd128Register, Simd128Register) \
V(F32x4Sqrt, Simd128Register, Simd128Register) \
V(F32x4Ceil, Simd128Register, Simd128Register) \
V(F32x4Floor, Simd128Register, Simd128Register) \
V(F32x4Trunc, Simd128Register, Simd128Register) \
V(F32x4NearestInt, Simd128Register, Simd128Register)
#define EMIT_SIMD_UNOP(name, dtype, stype) \ #define EMIT_SIMD_UNOP(name, dtype, stype) \
case kS390_##name: { \ case kS390_##name: { \
@ -2749,16 +2756,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
// vector unary ops // vector unary ops
case kS390_F32x4Abs: {
__ vfpso(i.OutputSimd128Register(), i.InputSimd128Register(0),
Condition(2), Condition(0), Condition(2));
break;
}
case kS390_F32x4Neg: {
__ vfpso(i.OutputSimd128Register(), i.InputSimd128Register(0),
Condition(0), Condition(0), Condition(2));
break;
}
case kS390_I64x2Neg: { case kS390_I64x2Neg: {
__ vlc(i.OutputSimd128Register(), i.InputSimd128Register(0), Condition(0), __ vlc(i.OutputSimd128Register(), i.InputSimd128Register(0), Condition(0),
Condition(0), Condition(3)); Condition(0), Condition(3));
@ -2799,11 +2796,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Condition(2)); Condition(2));
break; break;
} }
case kS390_F32x4Sqrt: {
__ vfsq(i.OutputSimd128Register(), i.InputSimd128Register(0),
Condition(0), Condition(0), Condition(2));
break;
}
case kS390_S128Not: { case kS390_S128Not: {
Simd128Register src = i.InputSimd128Register(0); Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register(); Simd128Register dst = i.OutputSimd128Register();
@ -3266,26 +3258,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Condition(3)); Condition(3));
break; break;
} }
case kS390_F32x4Ceil: {
__ vfi(i.OutputSimd128Register(), i.InputSimd128Register(0), Condition(6),
Condition(0), Condition(2));
break;
}
case kS390_F32x4Floor: {
__ vfi(i.OutputSimd128Register(), i.InputSimd128Register(0), Condition(7),
Condition(0), Condition(2));
break;
}
case kS390_F32x4Trunc: {
__ vfi(i.OutputSimd128Register(), i.InputSimd128Register(0), Condition(5),
Condition(0), Condition(2));
break;
}
case kS390_F32x4NearestInt: {
__ vfi(i.OutputSimd128Register(), i.InputSimd128Register(0), Condition(4),
Condition(0), Condition(2));
break;
}
case kS390_I32x4DotI16x8S: { case kS390_I32x4DotI16x8S: {
Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0)); Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
__ vme(kScratchDoubleReg, i.InputSimd128Register(0), __ vme(kScratchDoubleReg, i.InputSimd128Register(0),

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@ -2389,7 +2389,14 @@ SIMD_BINOP_RI_LIST(EMIT_SIMD_BINOP_RI)
V(f64x2_ceil, F64x2Ceil, fp, fp, true, bool) \ V(f64x2_ceil, F64x2Ceil, fp, fp, true, bool) \
V(f64x2_floor, F64x2Floor, fp, fp, true, bool) \ V(f64x2_floor, F64x2Floor, fp, fp, true, bool) \
V(f64x2_trunc, F64x2Trunc, fp, fp, true, bool) \ V(f64x2_trunc, F64x2Trunc, fp, fp, true, bool) \
V(f64x2_nearest_int, F64x2NearestInt, fp, fp, true, bool) V(f64x2_nearest_int, F64x2NearestInt, fp, fp, true, bool) \
V(f32x4_abs, F32x4Abs, fp, fp, , void) \
V(f32x4_neg, F32x4Neg, fp, fp, , void) \
V(f32x4_sqrt, F32x4Sqrt, fp, fp, , void) \
V(f32x4_ceil, F32x4Ceil, fp, fp, true, bool) \
V(f32x4_floor, F32x4Floor, fp, fp, true, bool) \
V(f32x4_trunc, F32x4Trunc, fp, fp, true, bool) \
V(f32x4_nearest_int, F32x4NearestInt, fp, fp, true, bool)
#define EMIT_SIMD_UNOP(name, op, dtype, stype, return_val, return_type) \ #define EMIT_SIMD_UNOP(name, op, dtype, stype, return_val, return_type) \
return_type LiftoffAssembler::emit_##name(LiftoffRegister dst, \ return_type LiftoffAssembler::emit_##name(LiftoffRegister dst, \
@ -2491,45 +2498,6 @@ void LiftoffAssembler::emit_f64x2_promote_low_f32x4(LiftoffRegister dst,
bailout(kSimd, "f64x2.promote_low_f32x4"); bailout(kSimd, "f64x2.promote_low_f32x4");
} }
void LiftoffAssembler::emit_f32x4_abs(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_f32x4_abs");
}
void LiftoffAssembler::emit_f32x4_neg(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_f32x4neg");
}
void LiftoffAssembler::emit_f32x4_sqrt(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_f32x4sqrt");
}
bool LiftoffAssembler::emit_f32x4_ceil(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "f32x4.ceil");
return true;
}
bool LiftoffAssembler::emit_f32x4_floor(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "f32x4.floor");
return true;
}
bool LiftoffAssembler::emit_f32x4_trunc(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "f32x4.trunc");
return true;
}
bool LiftoffAssembler::emit_f32x4_nearest_int(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "f32x4.nearest_int");
return true;
}
void LiftoffAssembler::emit_f32x4_pmin(LiftoffRegister dst, LiftoffRegister lhs, void LiftoffAssembler::emit_f32x4_pmin(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) { LiftoffRegister rhs) {
bailout(kSimd, "pmin unimplemented"); bailout(kSimd, "pmin unimplemented");