PPC/s390: [turbofan] Further optimize DataView accesses.
Port 5fecd146bf
Original Commit Message:
This adds support for unaligned load/store access to the DataView
backing store and uses byteswap operations to fix up the endianess
when necessary. This changes the Word32ReverseBytes operator to be
a required operator and adds the missing support on the Intel and
ARM platforms (on 64-bit platforms the Word64ReverseBytes operator
is also mandatory now).
This further improves the performance on the dataviewperf.js test
mentioned in the tracking bug by up to 40%, and at the same time
reduces the code complexity in the EffectControlLinearizer.
R=bmeurer@chromium.org, joransiu@ca.ibm.com, michael_dawson@ca.ibm.com
BUG=
LOG=N
Change-Id: Ia9aad21713a2ad76ce3ef2b816fc20e9a27fe4c9
Reviewed-on: https://chromium-review.googlesource.com/1174936
Reviewed-by: John Barboza <jbarboza@ca.ibm.com>
Commit-Queue: Junliang Yan <jyan@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#55132}
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@ -2058,6 +2058,35 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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ATOMIC_BINOP_CASE(Xor, xor_)
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#undef ATOMIC_BINOP_CASE
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case kPPC_ByteRev32: {
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Register input = i.InputRegister(0);
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Register output = i.OutputRegister();
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Register temp1 = r0;
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__ rotlwi(temp1, input, 8);
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__ rlwimi(temp1, input, 24, 0, 7);
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__ rlwimi(temp1, input, 24, 16, 23);
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__ extsw(output, temp1);
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break;
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}
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#ifdef V8_TARGET_ARCH_PPC64
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case kPPC_ByteRev64: {
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Register input = i.InputRegister(0);
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Register output = i.OutputRegister();
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Register temp1 = r0;
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Register temp2 = kScratchReg;
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Register temp3 = i.InputRegister(1);
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__ rldicl(temp1, input, 32, 32);
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__ rotlwi(temp2, input, 8);
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__ rlwimi(temp2, input, 24, 0, 7);
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__ rotlwi(temp3, temp1, 8);
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__ rlwimi(temp2, input, 24, 16, 23);
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__ rlwimi(temp3, temp1, 24, 0, 7);
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__ rlwimi(temp3, temp1, 24, 16, 23);
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__ rldicr(temp2, temp2, 32, 31);
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__ orx(output, temp2, temp3);
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break;
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}
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#endif // V8_TARGET_ARCH_PPC64
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default:
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UNREACHABLE();
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break;
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@ -124,7 +124,9 @@ namespace compiler {
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V(PPC_StoreWord32) \
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V(PPC_StoreWord64) \
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V(PPC_StoreFloat32) \
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V(PPC_StoreDouble)
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V(PPC_StoreDouble) \
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V(PPC_ByteRev32) \
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V(PPC_ByteRev64)
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// Addressing modes represent the "shape" of inputs to an instruction.
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// Many instructions support multiple addressing modes. Addressing modes
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@ -109,6 +109,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
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case kPPC_BitcastFloat32ToInt32:
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case kPPC_BitcastInt64ToDouble:
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case kPPC_BitcastDoubleToInt64:
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case kPPC_ByteRev32:
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case kPPC_ByteRev64:
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return kNoOpcodeFlags;
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case kPPC_LoadWordS8:
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@ -937,9 +937,17 @@ void InstructionSelector::VisitWord32ReverseBits(Node* node) { UNREACHABLE(); }
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void InstructionSelector::VisitWord64ReverseBits(Node* node) { UNREACHABLE(); }
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#endif
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void InstructionSelector::VisitWord64ReverseBytes(Node* node) { UNREACHABLE(); }
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void InstructionSelector::VisitWord64ReverseBytes(Node* node) {
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PPCOperandGenerator g(this);
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Emit(kPPC_ByteRev64, g.DefineAsRegister(node),
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g.UseRegister(node->InputAt(0)), g.TempRegister());
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}
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void InstructionSelector::VisitWord32ReverseBytes(Node* node) { UNREACHABLE(); }
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void InstructionSelector::VisitWord32ReverseBytes(Node* node) {
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PPCOperandGenerator g(this);
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Emit(kPPC_ByteRev32, g.DefineAsRegister(node),
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g.UseRegister(node->InputAt(0)));
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}
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void InstructionSelector::VisitSpeculationFence(Node* node) { UNREACHABLE(); }
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@ -2609,8 +2609,6 @@ InstructionSelector::SupportedMachineOperatorFlags() {
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MachineOperatorBuilder::kFloat64RoundTruncate |
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MachineOperatorBuilder::kFloat64RoundTiesAway |
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MachineOperatorBuilder::kWord32Popcnt |
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MachineOperatorBuilder::kWord32ReverseBytes |
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MachineOperatorBuilder::kWord64ReverseBytes |
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MachineOperatorBuilder::kInt32AbsWithOverflow |
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MachineOperatorBuilder::kInt64AbsWithOverflow |
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MachineOperatorBuilder::kWord64Popcnt;
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