PPC/s390: fix NAN propagation on float/double min and max
Using the proper `add` operation assures the NAN value is properly propagated to the result register. Change-Id: Icb86193f85534604f2a4a583d177a6f319ca38c3 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2429804 Reviewed-by: Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Farazmand <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#70127}
This commit is contained in:
Milad Fa
Commit Bot
parent
e487a7daa2
commit
1474e595cf
@ -449,41 +449,42 @@ void EmitWordLoadPoisoningIfNeeded(CodeGenerator* codegen, Instruction* instr,
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DCHECK_EQ(LeaveRC, i.OutputRCBit()); \
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} while (0)
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#define ASSEMBLE_FLOAT_MAX() \
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do { \
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DoubleRegister left_reg = i.InputDoubleRegister(0); \
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DoubleRegister right_reg = i.InputDoubleRegister(1); \
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DoubleRegister result_reg = i.OutputDoubleRegister(); \
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Label check_nan_left, check_zero, return_left, return_right, done; \
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__ fcmpu(left_reg, right_reg); \
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__ bunordered(&check_nan_left); \
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__ beq(&check_zero); \
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__ bge(&return_left); \
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__ b(&return_right); \
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\
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__ bind(&check_zero); \
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__ fcmpu(left_reg, kDoubleRegZero); \
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/* left == right != 0. */ \
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__ bne(&return_left); \
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/* At this point, both left and right are either 0 or -0. */ \
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__ fadd(result_reg, left_reg, right_reg); \
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__ b(&done); \
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\
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__ bind(&check_nan_left); \
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__ fcmpu(left_reg, left_reg); \
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/* left == NaN. */ \
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__ bunordered(&return_left); \
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__ bind(&return_right); \
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if (right_reg != result_reg) { \
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__ fmr(result_reg, right_reg); \
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} \
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__ b(&done); \
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\
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__ bind(&return_left); \
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if (left_reg != result_reg) { \
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__ fmr(result_reg, left_reg); \
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} \
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__ bind(&done); \
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#define ASSEMBLE_FLOAT_MAX() \
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do { \
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DoubleRegister left_reg = i.InputDoubleRegister(0); \
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DoubleRegister right_reg = i.InputDoubleRegister(1); \
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DoubleRegister result_reg = i.OutputDoubleRegister(); \
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Label check_zero, return_left, return_right, return_nan, done; \
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__ fcmpu(left_reg, right_reg); \
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__ bunordered(&return_nan); \
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__ beq(&check_zero); \
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__ bge(&return_left); \
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__ b(&return_right); \
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\
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__ bind(&check_zero); \
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__ fcmpu(left_reg, kDoubleRegZero); \
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/* left == right != 0. */ \
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__ bne(&return_left); \
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/* At this point, both left and right are either 0 or -0. */ \
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__ fadd(result_reg, left_reg, right_reg); \
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__ b(&done); \
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\
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__ bind(&return_nan); \
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/* If left or right are NaN, fadd propagates the appropriate one.*/ \
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__ fadd(result_reg, left_reg, right_reg); \
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__ b(&done); \
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\
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__ bind(&return_right); \
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if (right_reg != result_reg) { \
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__ fmr(result_reg, right_reg); \
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} \
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__ b(&done); \
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\
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__ bind(&return_left); \
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if (left_reg != result_reg) { \
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__ fmr(result_reg, left_reg); \
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} \
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__ bind(&done); \
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} while (0)
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#define ASSEMBLE_FLOAT_MIN() \
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@ -491,9 +492,9 @@ void EmitWordLoadPoisoningIfNeeded(CodeGenerator* codegen, Instruction* instr,
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DoubleRegister left_reg = i.InputDoubleRegister(0); \
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DoubleRegister right_reg = i.InputDoubleRegister(1); \
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DoubleRegister result_reg = i.OutputDoubleRegister(); \
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Label check_nan_left, check_zero, return_left, return_right, done; \
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Label check_zero, return_left, return_right, return_nan, done; \
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__ fcmpu(left_reg, right_reg); \
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__ bunordered(&check_nan_left); \
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__ bunordered(&return_nan); \
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__ beq(&check_zero); \
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__ ble(&return_left); \
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__ b(&return_right); \
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@ -515,10 +516,10 @@ void EmitWordLoadPoisoningIfNeeded(CodeGenerator* codegen, Instruction* instr,
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__ fneg(result_reg, result_reg); \
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__ b(&done); \
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\
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__ bind(&check_nan_left); \
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__ fcmpu(left_reg, left_reg); \
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/* left == NaN. */ \
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__ bunordered(&return_left); \
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__ bind(&return_nan); \
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/* If left or right are NaN, fadd propagates the appropriate one.*/ \
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__ fadd(result_reg, left_reg, right_reg); \
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__ b(&done); \
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\
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__ bind(&return_right); \
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if (right_reg != result_reg) { \
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@ -643,184 +643,184 @@ static inline int AssembleUnaryOp(Instruction* instr, _R _r, _M _m, _I _i) {
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__ MovFromFloatResult(i.OutputDoubleRegister()); \
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} while (0)
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#define ASSEMBLE_DOUBLE_MAX() \
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do { \
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DoubleRegister left_reg = i.InputDoubleRegister(0); \
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DoubleRegister right_reg = i.InputDoubleRegister(1); \
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DoubleRegister result_reg = i.OutputDoubleRegister(); \
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Label check_nan_left, check_zero, return_left, return_right, done; \
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__ cdbr(left_reg, right_reg); \
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__ bunordered(&check_nan_left, Label::kNear); \
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__ beq(&check_zero); \
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__ bge(&return_left, Label::kNear); \
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__ b(&return_right, Label::kNear); \
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\
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__ bind(&check_zero); \
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__ lzdr(kDoubleRegZero); \
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__ cdbr(left_reg, kDoubleRegZero); \
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/* left == right != 0. */ \
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__ bne(&return_left, Label::kNear); \
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/* At this point, both left and right are either 0 or -0. */ \
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/* N.B. The following works because +0 + -0 == +0 */ \
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/* For max we want logical-and of sign bit: (L + R) */ \
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__ ldr(result_reg, left_reg); \
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__ adbr(result_reg, right_reg); \
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__ b(&done, Label::kNear); \
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\
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__ bind(&check_nan_left); \
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__ cdbr(left_reg, left_reg); \
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/* left == NaN. */ \
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__ bunordered(&return_left, Label::kNear); \
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\
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__ bind(&return_right); \
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if (right_reg != result_reg) { \
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__ ldr(result_reg, right_reg); \
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} \
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__ b(&done, Label::kNear); \
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\
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__ bind(&return_left); \
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if (left_reg != result_reg) { \
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__ ldr(result_reg, left_reg); \
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} \
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__ bind(&done); \
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#define ASSEMBLE_DOUBLE_MAX() \
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do { \
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DoubleRegister left_reg = i.InputDoubleRegister(0); \
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DoubleRegister right_reg = i.InputDoubleRegister(1); \
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DoubleRegister result_reg = i.OutputDoubleRegister(); \
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Label check_zero, return_left, return_right, return_nan, done; \
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__ cdbr(left_reg, right_reg); \
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__ bunordered(&return_nan, Label::kNear); \
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__ beq(&check_zero); \
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__ bge(&return_left, Label::kNear); \
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__ b(&return_right, Label::kNear); \
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\
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__ bind(&check_zero); \
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__ lzdr(kDoubleRegZero); \
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__ cdbr(left_reg, kDoubleRegZero); \
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/* left == right != 0. */ \
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__ bne(&return_left, Label::kNear); \
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/* At this point, both left and right are either 0 or -0. */ \
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/* N.B. The following works because +0 + -0 == +0 */ \
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/* For max we want logical-and of sign bit: (L + R) */ \
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__ ldr(result_reg, left_reg); \
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__ adbr(result_reg, right_reg); \
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__ b(&done, Label::kNear); \
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\
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__ bind(&return_nan); \
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/* If left or right are NaN, adbr propagates the appropriate one.*/ \
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__ adbr(left_reg, right_reg); \
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__ b(&return_left, Label::kNear); \
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\
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__ bind(&return_right); \
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if (right_reg != result_reg) { \
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__ ldr(result_reg, right_reg); \
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} \
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__ b(&done, Label::kNear); \
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\
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__ bind(&return_left); \
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if (left_reg != result_reg) { \
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__ ldr(result_reg, left_reg); \
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} \
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__ bind(&done); \
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} while (0)
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#define ASSEMBLE_DOUBLE_MIN() \
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do { \
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DoubleRegister left_reg = i.InputDoubleRegister(0); \
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DoubleRegister right_reg = i.InputDoubleRegister(1); \
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DoubleRegister result_reg = i.OutputDoubleRegister(); \
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Label check_nan_left, check_zero, return_left, return_right, done; \
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__ cdbr(left_reg, right_reg); \
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__ bunordered(&check_nan_left, Label::kNear); \
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__ beq(&check_zero); \
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__ ble(&return_left, Label::kNear); \
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__ b(&return_right, Label::kNear); \
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\
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__ bind(&check_zero); \
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__ lzdr(kDoubleRegZero); \
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__ cdbr(left_reg, kDoubleRegZero); \
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/* left == right != 0. */ \
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__ bne(&return_left, Label::kNear); \
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/* At this point, both left and right are either 0 or -0. */ \
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/* N.B. The following works because +0 + -0 == +0 */ \
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/* For min we want logical-or of sign bit: -(-L + -R) */ \
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__ lcdbr(left_reg, left_reg); \
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__ ldr(result_reg, left_reg); \
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if (left_reg == right_reg) { \
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__ adbr(result_reg, right_reg); \
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} else { \
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__ sdbr(result_reg, right_reg); \
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} \
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__ lcdbr(result_reg, result_reg); \
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__ b(&done, Label::kNear); \
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\
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__ bind(&check_nan_left); \
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__ cdbr(left_reg, left_reg); \
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/* left == NaN. */ \
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__ bunordered(&return_left, Label::kNear); \
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\
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__ bind(&return_right); \
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if (right_reg != result_reg) { \
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__ ldr(result_reg, right_reg); \
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} \
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__ b(&done, Label::kNear); \
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\
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__ bind(&return_left); \
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if (left_reg != result_reg) { \
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__ ldr(result_reg, left_reg); \
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} \
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__ bind(&done); \
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#define ASSEMBLE_DOUBLE_MIN() \
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do { \
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DoubleRegister left_reg = i.InputDoubleRegister(0); \
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DoubleRegister right_reg = i.InputDoubleRegister(1); \
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DoubleRegister result_reg = i.OutputDoubleRegister(); \
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Label check_zero, return_left, return_right, return_nan, done; \
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__ cdbr(left_reg, right_reg); \
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__ bunordered(&return_nan, Label::kNear); \
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__ beq(&check_zero); \
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__ ble(&return_left, Label::kNear); \
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__ b(&return_right, Label::kNear); \
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\
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__ bind(&check_zero); \
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__ lzdr(kDoubleRegZero); \
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__ cdbr(left_reg, kDoubleRegZero); \
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/* left == right != 0. */ \
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__ bne(&return_left, Label::kNear); \
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/* At this point, both left and right are either 0 or -0. */ \
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/* N.B. The following works because +0 + -0 == +0 */ \
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/* For min we want logical-or of sign bit: -(-L + -R) */ \
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__ lcdbr(left_reg, left_reg); \
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__ ldr(result_reg, left_reg); \
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if (left_reg == right_reg) { \
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__ adbr(result_reg, right_reg); \
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} else { \
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__ sdbr(result_reg, right_reg); \
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} \
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__ lcdbr(result_reg, result_reg); \
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__ b(&done, Label::kNear); \
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\
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__ bind(&return_nan); \
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/* If left or right are NaN, adbr propagates the appropriate one.*/ \
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__ adbr(left_reg, right_reg); \
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__ b(&return_left, Label::kNear); \
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\
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__ bind(&return_right); \
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if (right_reg != result_reg) { \
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__ ldr(result_reg, right_reg); \
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} \
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__ b(&done, Label::kNear); \
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\
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__ bind(&return_left); \
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if (left_reg != result_reg) { \
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__ ldr(result_reg, left_reg); \
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} \
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__ bind(&done); \
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} while (0)
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#define ASSEMBLE_FLOAT_MAX() \
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do { \
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DoubleRegister left_reg = i.InputDoubleRegister(0); \
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DoubleRegister right_reg = i.InputDoubleRegister(1); \
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DoubleRegister result_reg = i.OutputDoubleRegister(); \
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Label check_nan_left, check_zero, return_left, return_right, done; \
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__ cebr(left_reg, right_reg); \
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__ bunordered(&check_nan_left, Label::kNear); \
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__ beq(&check_zero); \
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__ bge(&return_left, Label::kNear); \
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__ b(&return_right, Label::kNear); \
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\
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__ bind(&check_zero); \
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__ lzdr(kDoubleRegZero); \
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__ cebr(left_reg, kDoubleRegZero); \
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/* left == right != 0. */ \
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__ bne(&return_left, Label::kNear); \
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/* At this point, both left and right are either 0 or -0. */ \
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/* N.B. The following works because +0 + -0 == +0 */ \
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/* For max we want logical-and of sign bit: (L + R) */ \
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__ ldr(result_reg, left_reg); \
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__ aebr(result_reg, right_reg); \
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__ b(&done, Label::kNear); \
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\
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__ bind(&check_nan_left); \
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__ cebr(left_reg, left_reg); \
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/* left == NaN. */ \
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__ bunordered(&return_left, Label::kNear); \
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\
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__ bind(&return_right); \
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if (right_reg != result_reg) { \
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__ ldr(result_reg, right_reg); \
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} \
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__ b(&done, Label::kNear); \
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\
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__ bind(&return_left); \
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if (left_reg != result_reg) { \
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__ ldr(result_reg, left_reg); \
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} \
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__ bind(&done); \
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#define ASSEMBLE_FLOAT_MAX() \
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do { \
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DoubleRegister left_reg = i.InputDoubleRegister(0); \
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DoubleRegister right_reg = i.InputDoubleRegister(1); \
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DoubleRegister result_reg = i.OutputDoubleRegister(); \
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Label check_zero, return_left, return_right, return_nan, done; \
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__ cebr(left_reg, right_reg); \
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__ bunordered(&return_nan, Label::kNear); \
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__ beq(&check_zero); \
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__ bge(&return_left, Label::kNear); \
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__ b(&return_right, Label::kNear); \
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\
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__ bind(&check_zero); \
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__ lzdr(kDoubleRegZero); \
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__ cebr(left_reg, kDoubleRegZero); \
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/* left == right != 0. */ \
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__ bne(&return_left, Label::kNear); \
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/* At this point, both left and right are either 0 or -0. */ \
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/* N.B. The following works because +0 + -0 == +0 */ \
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/* For max we want logical-and of sign bit: (L + R) */ \
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__ ldr(result_reg, left_reg); \
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__ aebr(result_reg, right_reg); \
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__ b(&done, Label::kNear); \
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\
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__ bind(&return_nan); \
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/* If left or right are NaN, aebr propagates the appropriate one.*/ \
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__ aebr(left_reg, right_reg); \
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__ b(&return_left, Label::kNear); \
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\
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__ bind(&return_right); \
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if (right_reg != result_reg) { \
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__ ldr(result_reg, right_reg); \
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} \
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__ b(&done, Label::kNear); \
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\
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__ bind(&return_left); \
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if (left_reg != result_reg) { \
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__ ldr(result_reg, left_reg); \
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} \
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__ bind(&done); \
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} while (0)
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#define ASSEMBLE_FLOAT_MIN() \
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do { \
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DoubleRegister left_reg = i.InputDoubleRegister(0); \
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DoubleRegister right_reg = i.InputDoubleRegister(1); \
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DoubleRegister result_reg = i.OutputDoubleRegister(); \
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Label check_nan_left, check_zero, return_left, return_right, done; \
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__ cebr(left_reg, right_reg); \
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__ bunordered(&check_nan_left, Label::kNear); \
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__ beq(&check_zero); \
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__ ble(&return_left, Label::kNear); \
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__ b(&return_right, Label::kNear); \
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\
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__ bind(&check_zero); \
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__ lzdr(kDoubleRegZero); \
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__ cebr(left_reg, kDoubleRegZero); \
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/* left == right != 0. */ \
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__ bne(&return_left, Label::kNear); \
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/* At this point, both left and right are either 0 or -0. */ \
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/* N.B. The following works because +0 + -0 == +0 */ \
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/* For min we want logical-or of sign bit: -(-L + -R) */ \
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__ lcebr(left_reg, left_reg); \
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__ ldr(result_reg, left_reg); \
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if (left_reg == right_reg) { \
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__ aebr(result_reg, right_reg); \
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} else { \
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__ sebr(result_reg, right_reg); \
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} \
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__ lcebr(result_reg, result_reg); \
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__ b(&done, Label::kNear); \
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\
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__ bind(&check_nan_left); \
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__ cebr(left_reg, left_reg); \
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/* left == NaN. */ \
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__ bunordered(&return_left, Label::kNear); \
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\
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__ bind(&return_right); \
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if (right_reg != result_reg) { \
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__ ldr(result_reg, right_reg); \
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} \
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__ b(&done, Label::kNear); \
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\
|
||||
__ bind(&return_left); \
|
||||
if (left_reg != result_reg) { \
|
||||
__ ldr(result_reg, left_reg); \
|
||||
} \
|
||||
__ bind(&done); \
|
||||
#define ASSEMBLE_FLOAT_MIN() \
|
||||
do { \
|
||||
DoubleRegister left_reg = i.InputDoubleRegister(0); \
|
||||
DoubleRegister right_reg = i.InputDoubleRegister(1); \
|
||||
DoubleRegister result_reg = i.OutputDoubleRegister(); \
|
||||
Label check_zero, return_left, return_right, return_nan, done; \
|
||||
__ cebr(left_reg, right_reg); \
|
||||
__ bunordered(&return_nan, Label::kNear); \
|
||||
__ beq(&check_zero); \
|
||||
__ ble(&return_left, Label::kNear); \
|
||||
__ b(&return_right, Label::kNear); \
|
||||
\
|
||||
__ bind(&check_zero); \
|
||||
__ lzdr(kDoubleRegZero); \
|
||||
__ cebr(left_reg, kDoubleRegZero); \
|
||||
/* left == right != 0. */ \
|
||||
__ bne(&return_left, Label::kNear); \
|
||||
/* At this point, both left and right are either 0 or -0. */ \
|
||||
/* N.B. The following works because +0 + -0 == +0 */ \
|
||||
/* For min we want logical-or of sign bit: -(-L + -R) */ \
|
||||
__ lcebr(left_reg, left_reg); \
|
||||
__ ldr(result_reg, left_reg); \
|
||||
if (left_reg == right_reg) { \
|
||||
__ aebr(result_reg, right_reg); \
|
||||
} else { \
|
||||
__ sebr(result_reg, right_reg); \
|
||||
} \
|
||||
__ lcebr(result_reg, result_reg); \
|
||||
__ b(&done, Label::kNear); \
|
||||
\
|
||||
__ bind(&return_nan); \
|
||||
/* If left or right are NaN, aebr propagates the appropriate one.*/ \
|
||||
__ aebr(left_reg, right_reg); \
|
||||
__ b(&return_left, Label::kNear); \
|
||||
\
|
||||
__ bind(&return_right); \
|
||||
if (right_reg != result_reg) { \
|
||||
__ ldr(result_reg, right_reg); \
|
||||
} \
|
||||
__ b(&done, Label::kNear); \
|
||||
\
|
||||
__ bind(&return_left); \
|
||||
if (left_reg != result_reg) { \
|
||||
__ ldr(result_reg, left_reg); \
|
||||
} \
|
||||
__ bind(&done); \
|
||||
} while (0)
|
||||
//
|
||||
// Only MRI mode for these instructions available
|
||||
|
||||
Loading…
Reference in New Issue
Block a user