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[wasm-simd][x64] Add AVX for i64x2 shifts

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Bug: v8:9561
Change-Id: I6f0b027d02b4d6a128a81584d40a30b1c5c518f6
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2069399
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Cr-Commit-Position: refs/heads/master@{#66477}
This commit is contained in:
Ng Zhi An 2020-02-27 08:44:40 +00:00 committed by Commit Bot
parent eea168f8af
commit 169d336ec3
2 changed files with 10 additions and 6 deletions
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4
src/codegen/x64/macro-assembler-x64.h
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@ -197,7 +197,9 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
AVX_OP(Pavgb, pavgb)
AVX_OP(Pavgw, pavgw)
AVX_OP(Psrad, psrad)
AVX_OP(Psllq, psllq)
AVX_OP(Psrld, psrld)
AVX_OP(Psrlq, psrlq)
AVX_OP(Paddd, paddd)
AVX_OP(Paddq, paddq)
AVX_OP(Pcmpgtd, pcmpgtd)
@ -474,7 +476,9 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
void Pinsrb(XMMRegister dst, Register src, int8_t imm8);
void Pinsrb(XMMRegister dst, Operand src, int8_t imm8);
void Psllq(XMMRegister dst, int imm8) { Psllq(dst, static_cast<byte>(imm8)); }
void Psllq(XMMRegister dst, byte imm8);
void Psrlq(XMMRegister dst, int imm8) { Psrlq(dst, static_cast<byte>(imm8)); }
void Psrlq(XMMRegister dst, byte imm8);
void Pslld(XMMRegister dst, byte imm8);
void Psrld(XMMRegister dst, byte imm8);

12
src/compiler/backend/x64/code-generator-x64.cc
View File

@ -2654,7 +2654,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kX64I64x2Shl: {
// Take shift value modulo 2^6.
ASSEMBLE_SIMD_SHIFT(psllq, 6);
ASSEMBLE_SIMD_SHIFT(Psllq, 6);
break;
}
case kX64I64x2ShrS: {
@ -2667,14 +2667,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
// Modulo 64 not required as sarq_cl will mask cl to 6 bits.
// lower quadword
__ pextrq(tmp, src, 0x0);
__ Pextrq(tmp, src, static_cast<int8_t>(0x0));
__ sarq_cl(tmp);
__ pinsrq(dst, tmp, 0x0);
__ Pinsrq(dst, tmp, static_cast<int8_t>(0x0));
// upper quadword
__ pextrq(tmp, src, 0x1);
__ Pextrq(tmp, src, static_cast<int8_t>(0x1));
__ sarq_cl(tmp);
__ pinsrq(dst, tmp, 0x1);
__ Pinsrq(dst, tmp, static_cast<int8_t>(0x1));
break;
}
case kX64I64x2Add: {
@ -2804,7 +2804,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kX64I64x2ShrU: {
// Take shift value modulo 2^6.
ASSEMBLE_SIMD_SHIFT(psrlq, 6);
ASSEMBLE_SIMD_SHIFT(Psrlq, 6);
break;
}
case kX64I64x2MinU: {