AuroraMiddleware/v8
1
0
Fork 0
Code Issues 2 Pull Requests Releases Wiki Activity

ppc: [liftoff] implement multipication on liftoff

Browse Source 
Change-Id: Ibc2756484717804f67658156b750d9bbd18266fb
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3049352
Reviewed-by: Milad Fa <mfarazma@redhat.com>
Commit-Queue: Junliang Yan <junyan@redhat.com>
Cr-Commit-Position: refs/heads/master@{#75892}
This commit is contained in:
Junliang Yan 2021-07-23 11:33:56 -04:00 committed by V8 LUCI CQ
parent ef17601fa7
commit 1708ee634a
5 changed files with 49 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/codegen/ppc/assembler-ppc.cc
View File

@ -868,6 +868,10 @@ void Assembler::mullw(Register dst, Register src1, Register src2, OEBit o,
xo_form(EXT2 | MULLW, dst, src1, src2, o, r);
}
void Assembler::mulli(Register dst, Register src, const Operand& imm) {
d_form(MULLI, dst, src, imm.immediate(), true);
}
// Multiply hi word
void Assembler::mulhw(Register dst, Register src1, Register src2, RCBit r) {
xo_form(EXT2 | MULHWX, dst, src1, src2, LeaveOE, r);

1
src/codegen/ppc/assembler-ppc.h
View File

@ -827,6 +827,7 @@ class Assembler : public AssemblerBase {
void mulhw(Register dst, Register src1, Register src2, RCBit r = LeaveRC);
void mulhwu(Register dst, Register src1, Register src2, RCBit r = LeaveRC);
void mulli(Register dst, Register src, const Operand& imm);
void divw(Register dst, Register src1, Register src2, OEBit o = LeaveOE,
RCBit r = LeaveRC);

27
src/codegen/ppc/macro-assembler-ppc.cc
View File

@ -2730,6 +2730,33 @@ void TurboAssembler::SubS32(Register dst, Register src, const Operand& value,
extsw(dst, dst, r);
}
void TurboAssembler::MulS64(Register dst, Register src, const Operand& value,
Register scratch, OEBit s, RCBit r) {
if (is_int16(value.immediate()) && s == LeaveOE && r == LeaveRC) {
mulli(dst, src, value);
} else {
mov(scratch, value);
mulld(dst, src, scratch, s, r);
}
}
void TurboAssembler::MulS64(Register dst, Register src, Register value, OEBit s,
RCBit r) {
mulld(dst, src, value, s, r);
}
void TurboAssembler::MulS32(Register dst, Register src, const Operand& value,
Register scratch, OEBit s, RCBit r) {
MulS64(dst, src, value, scratch, s, r);
extsw(dst, dst, r);
}
void TurboAssembler::MulS32(Register dst, Register src, Register value, OEBit s,
RCBit r) {
MulS64(dst, src, value, s, r);
extsw(dst, dst, r);
}
void TurboAssembler::AndU64(Register dst, Register src, const Operand& value,
Register scratch, RCBit r) {
if (is_int16(value.immediate()) && r == SetRC) {

8
src/codegen/ppc/macro-assembler-ppc.h
View File

@ -185,6 +185,14 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
void SubS32(Register dst, Register src, const Operand& value,
Register scratch = r0, RCBit r = LeaveRC);
void SubS32(Register dst, Register src, Register value, RCBit r = LeaveRC);
void MulS64(Register dst, Register src, const Operand& value,
Register scratch = r0, OEBit s = LeaveOE, RCBit r = LeaveRC);
void MulS64(Register dst, Register src, Register value, OEBit s = LeaveOE,
RCBit r = LeaveRC);
void MulS32(Register dst, Register src, const Operand& value,
Register scratch = r0, OEBit s = LeaveOE, RCBit r = LeaveRC);
void MulS32(Register dst, Register src, Register value, OEBit s = LeaveOE,
RCBit r = LeaveRC);
void AndU64(Register dst, Register src, const Operand& value,
Register scratch = r0, RCBit r = SetRC);

20
src/wasm/baseline/ppc/liftoff-assembler-ppc.h
View File

@ -783,8 +783,6 @@ void LiftoffAssembler::FillStackSlotsWithZero(int start, int size) {
bailout(kUnsupportedArchitecture, "i64 shiftop: " #name); \
}
UNIMPLEMENTED_I32_BINOP(i32_mul)
UNIMPLEMENTED_I64_BINOP(i64_mul)
UNIMPLEMENTED_GP_UNOP(i32_clz)
UNIMPLEMENTED_GP_UNOP(i32_ctz)
UNIMPLEMENTED_FP_BINOP(f32_add)
@ -873,15 +871,15 @@ UNOP_LIST(EMIT_UNOP_FUNCTION)
V(i32_add, AddS32, Register, Register, Register, , , , USE, , void) \
V(i32_addi, AddS32, Register, Register, int32_t, , , Operand, USE, , void) \
V(i32_subi, SubS32, Register, Register, int32_t, , , Operand, USE, , void) \
V(i32_andi, AndU32, Register, Register, int32_t, , , Operand, SIGN_EXT, , \
void) \
V(i32_ori, OrU32, Register, Register, int32_t, , , Operand, SIGN_EXT, , \
void) \
V(i32_xori, XorU32, Register, Register, int32_t, , , Operand, SIGN_EXT, , \
void) \
V(i32_and, AndU32, Register, Register, Register, , , , SIGN_EXT, , void) \
V(i32_or, OrU32, Register, Register, Register, , , , SIGN_EXT, , void) \
V(i32_xor, XorU32, Register, Register, Register, , , , SIGN_EXT, , void) \
V(i32_mul, MulS32, Register, Register, Register, , , , USE, , void) \
V(i64_mul, MulS64, LiftoffRegister, LiftoffRegister, LiftoffRegister, \
LFR_TO_REG, LFR_TO_REG, LFR_TO_REG, USE, , void) \
V(i32_andi, AndU32, Register, Register, int32_t, , , Operand, USE, , void) \
V(i32_ori, OrU32, Register, Register, int32_t, , , Operand, USE, , void) \
V(i32_xori, XorU32, Register, Register, int32_t, , , Operand, USE, , void) \
V(i32_and, AndU32, Register, Register, Register, , , , USE, , void) \
V(i32_or, OrU32, Register, Register, Register, , , , USE, , void) \
V(i32_xor, XorU32, Register, Register, Register, , , , USE, , void) \
V(i64_and, AndU64, LiftoffRegister, LiftoffRegister, LiftoffRegister, \
LFR_TO_REG, LFR_TO_REG, LFR_TO_REG, USE, , void) \
V(i64_or, OrU64, LiftoffRegister, LiftoffRegister, LiftoffRegister, \