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[codegen][compiler] Rename ATOM to INTEL_ATOM to avoid shadow

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This shadows ATOM used in js-regxp.

Making this an enum class requires changing a lot of different places.

Atom is an Intel brand name, so INTEL_ATOM kinda make sense.

Bug: v8:12244,v8:12245
Change-Id: I80be342488328cde5aaca36f900375d2fb381253
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3276926
Reviewed-by: Maya Lekova <mslekova@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/main@{#77875}
This commit is contained in:
Ng Zhi An 2021-11-11 13:42:10 -08:00 committed by V8 LUCI CQ
parent 0bb4006648
commit 18311df345
7 changed files with 11 additions and 11 deletions
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2
src/codegen/cpu-features.h
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@ -26,7 +26,7 @@ enum CpuFeature {
BMI2,
LZCNT,
POPCNT,
ATOM,
INTEL_ATOM,
#elif V8_TARGET_ARCH_ARM
// - Standard configurations. The baseline is ARMv6+VFPv2.

6
src/codegen/ia32/assembler-ia32.cc
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@ -153,9 +153,9 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
if (cpu.has_lzcnt() && FLAG_enable_lzcnt) SetSupported(LZCNT);
if (cpu.has_popcnt() && FLAG_enable_popcnt) SetSupported(POPCNT);
if (strcmp(FLAG_mcpu, "auto") == 0) {
if (cpu.is_atom()) SetSupported(ATOM);
if (cpu.is_atom()) SetSupported(INTEL_ATOM);
} else if (strcmp(FLAG_mcpu, "atom") == 0) {
SetSupported(ATOM);
SetSupported(INTEL_ATOM);
}
// Ensure that supported cpu features make sense. E.g. it is wrong to support
@ -188,7 +188,7 @@ void CpuFeatures::PrintFeatures() {
CpuFeatures::IsSupported(AVX2), CpuFeatures::IsSupported(FMA3),
CpuFeatures::IsSupported(BMI1), CpuFeatures::IsSupported(BMI2),
CpuFeatures::IsSupported(LZCNT), CpuFeatures::IsSupported(POPCNT),
CpuFeatures::IsSupported(ATOM));
CpuFeatures::IsSupported(INTEL_ATOM));
}
// -----------------------------------------------------------------------------

2
src/codegen/shared-ia32-x64/macro-assembler-shared-ia32-x64.h
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@ -900,7 +900,7 @@ class V8_EXPORT_PRIVATE SharedTurboAssemblerBase : public SharedTurboAssembler {
vpshufb(dst, tmp1, dst);
vpshufb(tmp2, tmp1, tmp2);
vpaddb(dst, dst, tmp2);
} else if (CpuFeatures::IsSupported(ATOM)) {
} else if (CpuFeatures::IsSupported(INTEL_ATOM)) {
// Pre-Goldmont low-power Intel microarchitectures have very slow
// PSHUFB instruction, thus use PSHUFB-free divide-and-conquer
// algorithm on these processors. ATOM CPU feature captures exactly

6
src/codegen/x64/assembler-x64.cc
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@ -103,9 +103,9 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
if (cpu.has_lzcnt() && FLAG_enable_lzcnt) SetSupported(LZCNT);
if (cpu.has_popcnt() && FLAG_enable_popcnt) SetSupported(POPCNT);
if (strcmp(FLAG_mcpu, "auto") == 0) {
if (cpu.is_atom()) SetSupported(ATOM);
if (cpu.is_atom()) SetSupported(INTEL_ATOM);
} else if (strcmp(FLAG_mcpu, "atom") == 0) {
SetSupported(ATOM);
SetSupported(INTEL_ATOM);
}
// Ensure that supported cpu features make sense. E.g. it is wrong to support
@ -141,7 +141,7 @@ void CpuFeatures::PrintFeatures() {
CpuFeatures::IsSupported(AVX2), CpuFeatures::IsSupported(FMA3),
CpuFeatures::IsSupported(BMI1), CpuFeatures::IsSupported(BMI2),
CpuFeatures::IsSupported(LZCNT), CpuFeatures::IsSupported(POPCNT),
CpuFeatures::IsSupported(ATOM));
CpuFeatures::IsSupported(INTEL_ATOM));
}
// -----------------------------------------------------------------------------

2
src/codegen/x64/macro-assembler-x64.cc
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@ -1933,7 +1933,7 @@ void TurboAssembler::Call(ExternalReference ext) {
}
void TurboAssembler::Call(Operand op) {
if (!CpuFeatures::IsSupported(ATOM)) {
if (!CpuFeatures::IsSupported(INTEL_ATOM)) {
call(op);
} else {
movq(kScratchRegister, op);

2
src/compiler/backend/ia32/instruction-selector-ia32.cc
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@ -1461,7 +1461,7 @@ void InstructionSelector::EmitPrepareArguments(
stack_decrement = 0;
if (g.CanBeImmediate(input.node)) {
Emit(kIA32Push, g.NoOutput(), decrement, g.UseImmediate(input.node));
} else if (IsSupported(ATOM) ||
} else if (IsSupported(INTEL_ATOM) ||
sequence()->IsFP(GetVirtualRegister(input.node))) {
// TODO(bbudge): IA32Push cannot handle stack->stack double moves
// because there is no way to encode fixed double slots.

2
src/compiler/backend/x64/instruction-selector-x64.cc
View File

@ -1960,7 +1960,7 @@ void InstructionSelector::EmitPrepareArguments(
stack_decrement = 0;
if (g.CanBeImmediate(input.node)) {
Emit(kX64Push, g.NoOutput(), decrement, g.UseImmediate(input.node));
} else if (IsSupported(ATOM) ||
} else if (IsSupported(INTEL_ATOM) ||
sequence()->IsFP(GetVirtualRegister(input.node))) {
// TODO(titzer): X64Push cannot handle stack->stack double moves
// because there is no way to encode fixed double slots.