From 1835dec7c0b54ec50f4c99ddc9b19610f385a4d8 Mon Sep 17 00:00:00 2001 From: Milad Fa Date: Fri, 29 Jul 2022 14:13:52 -0400 Subject: [PATCH] PPC/s390: [wasm] Fix 64-bit addressed loads on arm64 Port 044a18ac248db67aaa5b04416f4ac88a28dfaa7f Original Commit Message: The {LiftoffAssembler::Load} method already receives an {i64_offset} parameter which skips the UXTW (zero extension of 32-bit addresses) in the memory operand. The same needs to happen on stores. On 32-bit platforms, we cannot have addresses >=4GB anyway (they would be detected as OOB before reaching the point in question), so this is not a problem. On x64, all 32-bit registers are zero-extended already (which is debug-checked in the generated code), so this is also no problem (and we just ignore the additional parameter). R=clemensb@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: Ic531618875bf3b6abcf3741bcbe153e603d9f250 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3794647 Reviewed-by: Clemens Backes Reviewed-by: Junliang Yan Commit-Queue: Milad Farazmand Cr-Commit-Position: refs/heads/main@{#82144} --- src/wasm/baseline/ppc/liftoff-assembler-ppc.h | 7 ++++++- src/wasm/baseline/s390/liftoff-assembler-s390.h | 15 ++++++++++++--- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/src/wasm/baseline/ppc/liftoff-assembler-ppc.h b/src/wasm/baseline/ppc/liftoff-assembler-ppc.h index 9362f9570d..da111ed054 100644 --- a/src/wasm/baseline/ppc/liftoff-assembler-ppc.h +++ b/src/wasm/baseline/ppc/liftoff-assembler-ppc.h @@ -447,7 +447,12 @@ void LiftoffAssembler::Load(LiftoffRegister dst, Register src_addr, void LiftoffAssembler::Store(Register dst_addr, Register offset_reg, uintptr_t offset_imm, LiftoffRegister src, StoreType type, LiftoffRegList pinned, - uint32_t* protected_store_pc, bool is_store_mem) { + uint32_t* protected_store_pc, bool is_store_mem, + bool i64_offset) { + if (!i64_offset && offset_reg != no_reg) { + ZeroExtWord32(ip, offset_reg); + offset_reg = ip; + } MemOperand dst_op = MemOperand(dst_addr, offset_reg, offset_imm); if (protected_store_pc) *protected_store_pc = pc_offset(); diff --git a/src/wasm/baseline/s390/liftoff-assembler-s390.h b/src/wasm/baseline/s390/liftoff-assembler-s390.h index 920341ae22..f03adb5dd8 100644 --- a/src/wasm/baseline/s390/liftoff-assembler-s390.h +++ b/src/wasm/baseline/s390/liftoff-assembler-s390.h @@ -422,11 +422,20 @@ void LiftoffAssembler::Load(LiftoffRegister dst, Register src_addr, void LiftoffAssembler::Store(Register dst_addr, Register offset_reg, uintptr_t offset_imm, LiftoffRegister src, StoreType type, LiftoffRegList /* pinned */, - uint32_t* protected_store_pc, bool is_store_mem) { + uint32_t* protected_store_pc, bool is_store_mem, + bool i64_offset) { + if (offset_reg != no_reg && !i64_offset) { + // Clear the upper 32 bits of the 64 bit offset register. + llgfr(ip, offset_reg); + offset_reg = ip; + } if (!is_int20(offset_imm)) { - mov(ip, Operand(offset_imm)); if (offset_reg != no_reg) { - AddS64(ip, offset_reg); + mov(r0, Operand(offset_imm)); + AddS64(r0, offset_reg); + mov(ip, r0); + } else { + mov(ip, Operand(offset_imm)); } offset_reg = ip; offset_imm = 0;