PPC: [wasm-simd] Add to simd conversion operations
Change-Id: I96b8b6735b4a1d8bb42040ecd9e46c5e97675749 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2298141 Reviewed-by: Junliang Yan <jyan@ca.ibm.com> Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com> Cr-Commit-Position: refs/heads/master@{#68870}
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@ -474,6 +474,10 @@ class Assembler : public AssemblerBase {
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const Simd128Register rb) { \
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vx_form(instr_name, rt, ra, rb); \
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}
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#define DECLARE_PPC_VX_INSTRUCTIONS_C_FORM(name, instr_name, instr_value) \
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inline void name(const Simd128Register rt, const Simd128Register rb) { \
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vx_form(instr_name, rt, rb); \
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}
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inline void vx_form(Instr instr, Simd128Register rt, Simd128Register rb,
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const Operand& imm) {
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@ -483,11 +487,16 @@ class Assembler : public AssemblerBase {
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Simd128Register rb) {
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emit(instr | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
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}
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inline void vx_form(Instr instr, Simd128Register rt, Simd128Register rb) {
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emit(instr | rt.code() * B21 | rb.code() * B11);
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}
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PPC_VX_OPCODE_A_FORM_LIST(DECLARE_PPC_VX_INSTRUCTIONS_A_FORM)
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PPC_VX_OPCODE_B_FORM_LIST(DECLARE_PPC_VX_INSTRUCTIONS_B_FORM)
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PPC_VX_OPCODE_C_FORM_LIST(DECLARE_PPC_VX_INSTRUCTIONS_C_FORM)
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#undef DECLARE_PPC_VX_INSTRUCTIONS_A_FORM
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#undef DECLARE_PPC_VX_INSTRUCTIONS_B_FORM
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#undef DECLARE_PPC_VX_INSTRUCTIONS_C_FORM
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#define DECLARE_PPC_VA_INSTRUCTIONS_A_FORM(name, instr_name, instr_value) \
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inline void name(const Simd128Register rt, const Simd128Register ra, \
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@ -2314,7 +2314,25 @@ using Instr = uint32_t;
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/* Vector Shift Right Algebraic Doubleword */ \
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V(vsrad, VSRAD, 0x100003C4) \
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/* Vector Logical AND */ \
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V(vand, VAND, 0x10000404)
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V(vand, VAND, 0x10000404) \
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/* Vector Pack Signed Word Signed Saturate */ \
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V(vpkswss, VPKSWSS, 0x100001CE) \
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/* Vector Pack Signed Word Unsigned Saturate */ \
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V(vpkswus, VPKSWUS, 0x1000014E) \
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/* Vector Pack Signed Halfword Signed Saturate */ \
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V(vpkshss, VPKSHSS, 0x1000018E) \
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/* Vector Pack Signed Halfword Unsigned Saturate */ \
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V(vpkshus, VPKSHUS, 0x1000010E)
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#define PPC_VX_OPCODE_C_FORM_LIST(V) \
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/* Vector Unpack Low Signed Halfword */ \
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V(vupklsh, VUPKLSH, 0x100002CE) \
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/* Vector Unpack High Signed Halfword */ \
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V(vupkhsh, VUPKHSH, 0x1000024E) \
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/* Vector Unpack Low Signed Byte */ \
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V(vupklsb, VUPKLSB, 0x1000028E) \
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/* Vector Unpack High Signed Byte */ \
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V(vupkhsb, VUPKHSB, 0x1000020E)
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#define PPC_VX_OPCODE_UNUSED_LIST(V) \
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/* Decimal Add Modulo */ \
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@ -2431,14 +2449,6 @@ using Instr = uint32_t;
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V(vpksdss, VPKSDSS, 0x100005CE) \
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/* Vector Pack Signed Doubleword Unsigned Saturate */ \
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V(vpksdus, VPKSDUS, 0x1000054E) \
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/* Vector Pack Signed Halfword Signed Saturate */ \
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V(vpkshss, VPKSHSS, 0x1000018E) \
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/* Vector Pack Signed Halfword Unsigned Saturate */ \
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V(vpkshus, VPKSHUS, 0x1000010E) \
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/* Vector Pack Signed Word Signed Saturate */ \
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V(vpkswss, VPKSWSS, 0x100001CE) \
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/* Vector Pack Signed Word Unsigned Saturate */ \
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V(vpkswus, VPKSWUS, 0x1000014E) \
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/* Vector Pack Unsigned Doubleword Unsigned Saturate */ \
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V(vpkudus, VPKUDUS, 0x100004CE) \
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/* Vector Pack Unsigned Halfword Unsigned Saturate */ \
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@ -2517,18 +2527,10 @@ using Instr = uint32_t;
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V(vsumsws, VSUMSWS, 0x10000788) \
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/* Vector Unpack High Pixel */ \
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V(vupkhpx, VUPKHPX, 0x1000034E) \
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/* Vector Unpack High Signed Byte */ \
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V(vupkhsb, VUPKHSB, 0x1000020E) \
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/* Vector Unpack High Signed Halfword */ \
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V(vupkhsh, VUPKHSH, 0x1000024E) \
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/* Vector Unpack High Signed Word */ \
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V(vupkhsw, VUPKHSW, 0x1000064E) \
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/* Vector Unpack Low Pixel */ \
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V(vupklpx, VUPKLPX, 0x100003CE) \
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/* Vector Unpack Low Signed Byte */ \
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V(vupklsb, VUPKLSB, 0x1000028E) \
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/* Vector Unpack Low Signed Halfword */ \
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V(vupklsh, VUPKLSH, 0x100002CE) \
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/* Vector Unpack Low Signed Word */ \
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V(vupklsw, VUPKLSW, 0x100006CE) \
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/* Vector AES Cipher */ \
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@ -2553,6 +2555,7 @@ using Instr = uint32_t;
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#define PPC_VX_OPCODE_LIST(V) \
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PPC_VX_OPCODE_A_FORM_LIST(V) \
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PPC_VX_OPCODE_B_FORM_LIST(V) \
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PPC_VX_OPCODE_C_FORM_LIST(V) \
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PPC_VX_OPCODE_UNUSED_LIST(V)
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#define PPC_XS_OPCODE_LIST(V) \
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@ -3072,14 +3072,89 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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}
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case kPPC_F32x4SConvertI32x4: {
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__ xvcvsxwsp(i.OutputSimd128Register(), i.InputSimd128Register(0));
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break;
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}
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case kPPC_F32x4UConvertI32x4: {
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__ xvcvuxwsp(i.OutputSimd128Register(), i.InputSimd128Register(0));
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break;
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}
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case kPPC_I32x4SConvertI16x8Low: {
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__ vupklsh(i.OutputSimd128Register(), i.InputSimd128Register(0));
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break;
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}
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case kPPC_I32x4SConvertI16x8High: {
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__ vupkhsh(i.OutputSimd128Register(), i.InputSimd128Register(0));
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break;
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}
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case kPPC_I32x4UConvertI16x8Low: {
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__ vupklsh(i.OutputSimd128Register(), i.InputSimd128Register(0));
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// Zero extend.
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__ mov(ip, Operand(0xFFFF));
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__ mtvsrd(kScratchDoubleReg, ip);
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__ vspltw(kScratchDoubleReg, kScratchDoubleReg, Operand(1));
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__ vand(i.OutputSimd128Register(), kScratchDoubleReg,
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i.OutputSimd128Register());
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break;
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}
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case kPPC_I32x4UConvertI16x8High: {
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__ vupkhsh(i.OutputSimd128Register(), i.InputSimd128Register(0));
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// Zero extend.
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__ mov(ip, Operand(0xFFFF));
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__ mtvsrd(kScratchDoubleReg, ip);
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__ vspltw(kScratchDoubleReg, kScratchDoubleReg, Operand(1));
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__ vand(i.OutputSimd128Register(), kScratchDoubleReg,
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i.OutputSimd128Register());
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break;
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}
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case kPPC_I16x8SConvertI8x16Low: {
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__ vupklsb(i.OutputSimd128Register(), i.InputSimd128Register(0));
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break;
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}
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case kPPC_I16x8SConvertI8x16High: {
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__ vupkhsb(i.OutputSimd128Register(), i.InputSimd128Register(0));
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break;
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}
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case kPPC_I16x8UConvertI8x16Low: {
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__ vupklsb(i.OutputSimd128Register(), i.InputSimd128Register(0));
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// Zero extend.
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__ li(ip, Operand(0xFF));
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__ mtvsrd(kScratchDoubleReg, ip);
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__ vsplth(kScratchDoubleReg, kScratchDoubleReg, Operand(3));
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__ vand(i.OutputSimd128Register(), kScratchDoubleReg,
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i.OutputSimd128Register());
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break;
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}
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case kPPC_I16x8UConvertI8x16High: {
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__ vupkhsb(i.OutputSimd128Register(), i.InputSimd128Register(0));
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// Zero extend.
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__ li(ip, Operand(0xFF));
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__ mtvsrd(kScratchDoubleReg, ip);
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__ vsplth(kScratchDoubleReg, kScratchDoubleReg, Operand(3));
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__ vand(i.OutputSimd128Register(), kScratchDoubleReg,
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i.OutputSimd128Register());
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break;
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}
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case kPPC_I16x8SConvertI32x4: {
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__ vpkswss(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kPPC_I16x8UConvertI32x4: {
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__ vpkswus(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kPPC_I8x16SConvertI16x8: {
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__ vpkshss(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kPPC_I8x16UConvertI16x8: {
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__ vpkshus(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kPPC_StoreCompressTagged: {
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ASSEMBLE_STORE_INTEGER(StoreTaggedField, StoreTaggedFieldX);
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break;
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@ -265,6 +265,10 @@ namespace compiler {
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V(PPC_I32x4Abs) \
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V(PPC_I32x4SConvertF32x4) \
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V(PPC_I32x4UConvertF32x4) \
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V(PPC_I32x4SConvertI16x8Low) \
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V(PPC_I32x4SConvertI16x8High) \
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V(PPC_I32x4UConvertI16x8Low) \
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V(PPC_I32x4UConvertI16x8High) \
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V(PPC_I16x8Splat) \
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V(PPC_I16x8ExtractLaneU) \
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V(PPC_I16x8ExtractLaneS) \
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@ -288,6 +292,12 @@ namespace compiler {
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V(PPC_I16x8ShrU) \
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V(PPC_I16x8Neg) \
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V(PPC_I16x8Abs) \
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V(PPC_I16x8SConvertI32x4) \
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V(PPC_I16x8UConvertI32x4) \
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V(PPC_I16x8SConvertI8x16Low) \
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V(PPC_I16x8SConvertI8x16High) \
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V(PPC_I16x8UConvertI8x16Low) \
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V(PPC_I16x8UConvertI8x16High) \
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V(PPC_I8x16Splat) \
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V(PPC_I8x16ExtractLaneU) \
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V(PPC_I8x16ExtractLaneS) \
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@ -310,6 +320,8 @@ namespace compiler {
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V(PPC_I8x16ShrU) \
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V(PPC_I8x16Neg) \
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V(PPC_I8x16Abs) \
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V(PPC_I8x16SConvertI16x8) \
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V(PPC_I8x16UConvertI16x8) \
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V(PPC_V64x2AnyTrue) \
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V(PPC_V32x4AnyTrue) \
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V(PPC_V16x8AnyTrue) \
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@ -188,6 +188,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
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case kPPC_I32x4Abs:
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case kPPC_I32x4SConvertF32x4:
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case kPPC_I32x4UConvertF32x4:
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case kPPC_I32x4SConvertI16x8Low:
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case kPPC_I32x4SConvertI16x8High:
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case kPPC_I32x4UConvertI16x8Low:
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case kPPC_I32x4UConvertI16x8High:
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case kPPC_I16x8Splat:
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case kPPC_I16x8ExtractLaneU:
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case kPPC_I16x8ExtractLaneS:
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@ -211,6 +215,12 @@ int InstructionScheduler::GetTargetInstructionFlags(
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case kPPC_I16x8ShrU:
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case kPPC_I16x8Neg:
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case kPPC_I16x8Abs:
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case kPPC_I16x8SConvertI32x4:
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case kPPC_I16x8UConvertI32x4:
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case kPPC_I16x8SConvertI8x16Low:
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case kPPC_I16x8SConvertI8x16High:
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case kPPC_I16x8UConvertI8x16Low:
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case kPPC_I16x8UConvertI8x16High:
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case kPPC_I8x16Splat:
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case kPPC_I8x16ExtractLaneU:
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case kPPC_I8x16ExtractLaneS:
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@ -233,6 +243,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
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case kPPC_I8x16ShrU:
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case kPPC_I8x16Neg:
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case kPPC_I8x16Abs:
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case kPPC_I8x16SConvertI16x8:
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case kPPC_I8x16UConvertI16x8:
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case kPPC_V64x2AnyTrue:
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case kPPC_V32x4AnyTrue:
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case kPPC_V16x8AnyTrue:
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@ -2179,6 +2179,8 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
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V(I16x8GeS) \
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V(I16x8GtU) \
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V(I16x8GeU) \
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V(I16x8SConvertI32x4) \
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V(I16x8UConvertI32x4) \
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V(I8x16Add) \
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V(I8x16Sub) \
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V(I8x16Mul) \
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@ -2192,26 +2194,40 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
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V(I8x16GeS) \
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V(I8x16GtU) \
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V(I8x16GeU) \
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V(I8x16SConvertI16x8) \
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V(I8x16UConvertI16x8) \
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V(S128And) \
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V(S128Or) \
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V(S128Xor)
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#define SIMD_UNOP_LIST(V) \
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V(F64x2Abs) \
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V(F64x2Neg) \
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V(F64x2Sqrt) \
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V(F32x4Abs) \
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V(F32x4Neg) \
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V(F32x4RecipApprox) \
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V(F32x4RecipSqrtApprox) \
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V(F32x4Sqrt) \
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V(I64x2Neg) \
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V(I32x4Neg) \
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V(I32x4Abs) \
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V(I16x8Neg) \
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V(I16x8Abs) \
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V(I8x16Neg) \
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V(I8x16Abs) \
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#define SIMD_UNOP_LIST(V) \
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V(F64x2Abs) \
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V(F64x2Neg) \
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V(F64x2Sqrt) \
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V(F32x4Abs) \
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V(F32x4Neg) \
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V(F32x4RecipApprox) \
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V(F32x4RecipSqrtApprox) \
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V(F32x4Sqrt) \
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V(F32x4SConvertI32x4) \
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V(F32x4UConvertI32x4) \
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V(I64x2Neg) \
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V(I32x4Neg) \
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V(I32x4Abs) \
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V(I32x4SConvertF32x4) \
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V(I32x4UConvertF32x4) \
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V(I32x4SConvertI16x8Low) \
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V(I32x4SConvertI16x8High) \
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V(I32x4UConvertI16x8Low) \
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V(I32x4UConvertI16x8High) \
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V(I16x8Neg) \
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V(I16x8Abs) \
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V(I8x16Neg) \
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V(I8x16Abs) \
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V(I16x8SConvertI8x16Low) \
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V(I16x8SConvertI8x16High) \
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V(I16x8UConvertI8x16Low) \
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V(I16x8UConvertI8x16High) \
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V(S128Not)
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#define SIMD_SHIFT_LIST(V) \
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@ -2236,12 +2252,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
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V(V16x8AllTrue) \
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V(V8x16AllTrue)
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#define SIMD_CONVERSION_LIST(V) \
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V(I32x4SConvertF32x4) \
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V(I32x4UConvertF32x4) \
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V(F32x4SConvertI32x4) \
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V(F32x4UConvertI32x4)
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#define SIMD_VISIT_SPLAT(Type) \
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void InstructionSelector::Visit##Type##Splat(Node* node) { \
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PPCOperandGenerator g(this); \
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@ -2322,16 +2332,6 @@ SIMD_SHIFT_LIST(SIMD_VISIT_SHIFT)
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SIMD_BOOL_LIST(SIMD_VISIT_BOOL)
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#undef SIMD_VISIT_BOOL
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#undef SIMD_BOOL_LIST
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#define SIMD_VISIT_CONVERSION(Opcode) \
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void InstructionSelector::Visit##Opcode(Node* node) { \
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PPCOperandGenerator g(this); \
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Emit(kPPC_##Opcode, g.DefineAsRegister(node), \
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g.UseRegister(node->InputAt(0))); \
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}
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SIMD_CONVERSION_LIST(SIMD_VISIT_CONVERSION)
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#undef SIMD_VISIT_CONVERSION
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#undef SIMD_CONVERSION_LIST
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#undef SIMD_TYPES
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void InstructionSelector::VisitS128Zero(Node* node) {
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@ -2419,53 +2419,6 @@ void InstructionSelector::VisitF32x4Min(Node* node) { UNIMPLEMENTED(); }
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void InstructionSelector::VisitF32x4Max(Node* node) { UNIMPLEMENTED(); }
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void InstructionSelector::VisitI32x4SConvertI16x8Low(Node* node) {
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UNIMPLEMENTED();
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}
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void InstructionSelector::VisitI32x4SConvertI16x8High(Node* node) {
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UNIMPLEMENTED();
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}
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void InstructionSelector::VisitI32x4UConvertI16x8Low(Node* node) {
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UNIMPLEMENTED();
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}
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||||
|
||||
void InstructionSelector::VisitI32x4UConvertI16x8High(Node* node) {
|
||||
UNIMPLEMENTED();
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitI16x8SConvertI8x16Low(Node* node) {
|
||||
UNIMPLEMENTED();
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitI16x8SConvertI8x16High(Node* node) {
|
||||
UNIMPLEMENTED();
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitI16x8UConvertI8x16Low(Node* node) {
|
||||
UNIMPLEMENTED();
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitI16x8UConvertI8x16High(Node* node) {
|
||||
UNIMPLEMENTED();
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitI16x8SConvertI32x4(Node* node) {
|
||||
UNIMPLEMENTED();
|
||||
}
|
||||
void InstructionSelector::VisitI16x8UConvertI32x4(Node* node) {
|
||||
UNIMPLEMENTED();
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitI8x16SConvertI16x8(Node* node) {
|
||||
UNIMPLEMENTED();
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitI8x16UConvertI16x8(Node* node) {
|
||||
UNIMPLEMENTED();
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitS8x16Shuffle(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitS8x16Swizzle(Node* node) { UNIMPLEMENTED(); }
|
||||
|
Loading…
Reference in New Issue
Block a user