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S390[liftoff]: Pass scratch registers where needed

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This CL assures scratch registers are passed where needed
and cleans up Simd functions shared between TF and LO.

Change-Id: Ib7633e0d51f3aa92d2bcdfc69d0efe779062af62
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3489239
Reviewed-by: Junliang Yan <junyan@redhat.com>
Commit-Queue: Milad Farazmand <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/main@{#79295}
This commit is contained in:
Milad Fa 2022-02-25 11:35:40 -05:00 committed by V8 LUCI CQ
parent c6602004a6
commit 19ea55f897
4 changed files with 446 additions and 384 deletions
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129
src/codegen/s390/macro-assembler-s390.cc
View File

@ -5153,8 +5153,6 @@ void TurboAssembler::AtomicExchangeU16(Register addr, Register value,
}
// Simd Support.
#define kScratchDoubleReg d13
void TurboAssembler::F64x2Splat(Simd128Register dst, Simd128Register src) {
vrep(dst, src, Operand(0), Condition(3));
}
@ -5184,69 +5182,70 @@ void TurboAssembler::I8x16Splat(Simd128Register dst, Register src) {
}
void TurboAssembler::F64x2ExtractLane(DoubleRegister dst, Simd128Register src,
uint8_t imm_lane_idx) {
uint8_t imm_lane_idx, Register) {
vrep(dst, src, Operand(1 - imm_lane_idx), Condition(3));
}
void TurboAssembler::F32x4ExtractLane(DoubleRegister dst, Simd128Register src,
uint8_t imm_lane_idx) {
uint8_t imm_lane_idx, Register) {
vrep(dst, src, Operand(3 - imm_lane_idx), Condition(2));
}
void TurboAssembler::I64x2ExtractLane(Register dst, Simd128Register src,
uint8_t imm_lane_idx) {
uint8_t imm_lane_idx, Register) {
vlgv(dst, src, MemOperand(r0, 1 - imm_lane_idx), Condition(3));
}
void TurboAssembler::I32x4ExtractLane(Register dst, Simd128Register src,
uint8_t imm_lane_idx) {
uint8_t imm_lane_idx, Register) {
vlgv(dst, src, MemOperand(r0, 3 - imm_lane_idx), Condition(2));
}
void TurboAssembler::I16x8ExtractLaneU(Register dst, Simd128Register src,
uint8_t imm_lane_idx) {
uint8_t imm_lane_idx, Register) {
vlgv(dst, src, MemOperand(r0, 7 - imm_lane_idx), Condition(1));
}
void TurboAssembler::I16x8ExtractLaneS(Register dst, Simd128Register src,
uint8_t imm_lane_idx) {
vlgv(r0, src, MemOperand(r0, 7 - imm_lane_idx), Condition(1));
lghr(dst, r0);
uint8_t imm_lane_idx, Register scratch) {
vlgv(scratch, src, MemOperand(r0, 7 - imm_lane_idx), Condition(1));
lghr(dst, scratch);
}
void TurboAssembler::I8x16ExtractLaneU(Register dst, Simd128Register src,
uint8_t imm_lane_idx) {
uint8_t imm_lane_idx, Register) {
vlgv(dst, src, MemOperand(r0, 15 - imm_lane_idx), Condition(0));
}
void TurboAssembler::I8x16ExtractLaneS(Register dst, Simd128Register src,
uint8_t imm_lane_idx) {
vlgv(r0, src, MemOperand(r0, 15 - imm_lane_idx), Condition(0));
lgbr(dst, r0);
uint8_t imm_lane_idx, Register scratch) {
vlgv(scratch, src, MemOperand(r0, 15 - imm_lane_idx), Condition(0));
lgbr(dst, scratch);
}
void TurboAssembler::F64x2ReplaceLane(Simd128Register dst, Simd128Register src1,
DoubleRegister src2,
uint8_t imm_lane_idx) {
vlgv(r0, src2, MemOperand(r0, 0), Condition(3));
DoubleRegister src2, uint8_t imm_lane_idx,
Register scratch) {
vlgv(scratch, src2, MemOperand(r0, 0), Condition(3));
if (src1 != dst) {
vlr(dst, src1, Condition(0), Condition(0), Condition(0));
}
vlvg(dst, r0, MemOperand(r0, 1 - imm_lane_idx), Condition(3));
vlvg(dst, scratch, MemOperand(r0, 1 - imm_lane_idx), Condition(3));
}
void TurboAssembler::F32x4ReplaceLane(Simd128Register dst, Simd128Register src1,
DoubleRegister src2,
uint8_t imm_lane_idx) {
vlgv(r0, src2, MemOperand(r0, 0), Condition(2));
DoubleRegister src2, uint8_t imm_lane_idx,
Register scratch) {
vlgv(scratch, src2, MemOperand(r0, 0), Condition(2));
if (src1 != dst) {
vlr(dst, src1, Condition(0), Condition(0), Condition(0));
}
vlvg(dst, r0, MemOperand(r0, 3 - imm_lane_idx), Condition(2));
vlvg(dst, scratch, MemOperand(r0, 3 - imm_lane_idx), Condition(2));
}
void TurboAssembler::I64x2ReplaceLane(Simd128Register dst, Simd128Register src1,
Register src2, uint8_t imm_lane_idx) {
Register src2, uint8_t imm_lane_idx,
Register) {
if (src1 != dst) {
vlr(dst, src1, Condition(0), Condition(0), Condition(0));
}
@ -5254,7 +5253,8 @@ void TurboAssembler::I64x2ReplaceLane(Simd128Register dst, Simd128Register src1,
}
void TurboAssembler::I32x4ReplaceLane(Simd128Register dst, Simd128Register src1,
Register src2, uint8_t imm_lane_idx) {
Register src2, uint8_t imm_lane_idx,
Register) {
if (src1 != dst) {
vlr(dst, src1, Condition(0), Condition(0), Condition(0));
}
@ -5262,7 +5262,8 @@ void TurboAssembler::I32x4ReplaceLane(Simd128Register dst, Simd128Register src1,
}
void TurboAssembler::I16x8ReplaceLane(Simd128Register dst, Simd128Register src1,
Register src2, uint8_t imm_lane_idx) {
Register src2, uint8_t imm_lane_idx,
Register) {
if (src1 != dst) {
vlr(dst, src1, Condition(0), Condition(0), Condition(0));
}
@ -5270,7 +5271,8 @@ void TurboAssembler::I16x8ReplaceLane(Simd128Register dst, Simd128Register src1,
}
void TurboAssembler::I8x16ReplaceLane(Simd128Register dst, Simd128Register src1,
Register src2, uint8_t imm_lane_idx) {
Register src2, uint8_t imm_lane_idx,
Register) {
if (src1 != dst) {
vlr(dst, src1, Condition(0), Condition(0), Condition(0));
}
@ -5434,16 +5436,16 @@ SIMD_BINOP_LIST_VRR_C(EMIT_SIMD_BINOP_VRR_C)
#define EMIT_SIMD_SHIFT(name, op, c1) \
void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \
Register src2) { \
vlvg(kScratchDoubleReg, src2, MemOperand(r0, 0), Condition(c1)); \
vrep(kScratchDoubleReg, kScratchDoubleReg, Operand(0), Condition(c1)); \
op(dst, src1, kScratchDoubleReg, Condition(0), Condition(0), \
Condition(c1)); \
Register src2, Simd128Register scratch) { \
vlvg(scratch, src2, MemOperand(r0, 0), Condition(c1)); \
vrep(scratch, scratch, Operand(0), Condition(c1)); \
op(dst, src1, scratch, Condition(0), Condition(0), Condition(c1)); \
} \
void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \
const Operand& src2) { \
mov(ip, src2); \
name(dst, src1, ip); \
const Operand& src2, Register scratch1, \
Simd128Register scratch2) { \
mov(scratch1, src2); \
name(dst, src1, scratch1, scratch2); \
}
SIMD_SHIFT_LIST(EMIT_SIMD_SHIFT)
#undef EMIT_SIMD_SHIFT
@ -5512,17 +5514,18 @@ SIMD_QFM_LIST(EMIT_SIMD_QFM)
#undef SIMD_QFM_LIST
void TurboAssembler::I64x2Mul(Simd128Register dst, Simd128Register src1,
Simd128Register src2) {
Register scratch_1 = r0;
Register scratch_2 = r1;
Simd128Register src2, Register scratch1,
Register scratch2, Register scratch3) {
Register scratch_1 = scratch1;
Register scratch_2 = scratch2;
for (int i = 0; i < 2; i++) {
vlgv(scratch_1, src1, MemOperand(r0, i), Condition(3));
vlgv(scratch_2, src2, MemOperand(r0, i), Condition(3));
MulS64(scratch_1, scratch_2);
scratch_1 = r1;
scratch_2 = ip;
scratch_1 = scratch2;
scratch_2 = scratch3;
}
vlvgp(dst, r0, r1);
vlvgp(dst, scratch1, scratch2);
}
void TurboAssembler::F64x2Ne(Simd128Register dst, Simd128Register src1,
@ -5584,10 +5587,10 @@ void TurboAssembler::I32x4GeS(Simd128Register dst, Simd128Register src1,
}
void TurboAssembler::I32x4GeU(Simd128Register dst, Simd128Register src1,
Simd128Register src2) {
vceq(kScratchDoubleReg, src1, src2, Condition(0), Condition(2));
Simd128Register src2, Simd128Register scratch) {
vceq(scratch, src1, src2, Condition(0), Condition(2));
vchl(dst, src1, src2, Condition(0), Condition(2));
vo(dst, dst, kScratchDoubleReg, Condition(0), Condition(0), Condition(2));
vo(dst, dst, scratch, Condition(0), Condition(0), Condition(2));
}
void TurboAssembler::I16x8Ne(Simd128Register dst, Simd128Register src1,
@ -5604,10 +5607,10 @@ void TurboAssembler::I16x8GeS(Simd128Register dst, Simd128Register src1,
}
void TurboAssembler::I16x8GeU(Simd128Register dst, Simd128Register src1,
Simd128Register src2) {
vceq(kScratchDoubleReg, src1, src2, Condition(0), Condition(1));
Simd128Register src2, Simd128Register scratch) {
vceq(scratch, src1, src2, Condition(0), Condition(1));
vchl(dst, src1, src2, Condition(0), Condition(1));
vo(dst, dst, kScratchDoubleReg, Condition(0), Condition(0), Condition(1));
vo(dst, dst, scratch, Condition(0), Condition(0), Condition(1));
}
void TurboAssembler::I8x16Ne(Simd128Register dst, Simd128Register src1,
@ -5624,10 +5627,10 @@ void TurboAssembler::I8x16GeS(Simd128Register dst, Simd128Register src1,
}
void TurboAssembler::I8x16GeU(Simd128Register dst, Simd128Register src1,
Simd128Register src2) {
vceq(kScratchDoubleReg, src1, src2, Condition(0), Condition(0));
Simd128Register src2, Simd128Register scratch) {
vceq(scratch, src1, src2, Condition(0), Condition(0));
vchl(dst, src1, src2, Condition(0), Condition(0));
vo(dst, dst, kScratchDoubleReg, Condition(0), Condition(0), Condition(0));
vo(dst, dst, scratch, Condition(0), Condition(0), Condition(0));
}
void TurboAssembler::I64x2BitMask(Register dst, Simd128Register src,
@ -5978,23 +5981,23 @@ void TurboAssembler::S128Const(Simd128Register dst, uint64_t high, uint64_t low,
}
void TurboAssembler::I8x16Swizzle(Simd128Register dst, Simd128Register src1,
Simd128Register src2,
Simd128Register scratch1,
Simd128Register scratch2) {
Simd128Register src2, Register scratch1,
Register scratch2, Simd128Register scratch3,
Simd128Register scratch4) {
DCHECK_NE(src1, scratch2);
// Saturate the indices to 5 bits. Input indices more than 31 should
// return 0.
vrepi(scratch1, Operand(31), Condition(0));
vmnl(scratch2, src2, scratch1, Condition(0), Condition(0), Condition(0));
vrepi(scratch3, Operand(31), Condition(0));
vmnl(scratch4, src2, scratch3, Condition(0), Condition(0), Condition(0));
// Input needs to be reversed.
vlgv(r0, src1, MemOperand(r0, 0), Condition(3));
vlgv(r1, src1, MemOperand(r0, 1), Condition(3));
lrvgr(r0, r0);
lrvgr(r1, r1);
vlvgp(dst, r1, r0);
vlgv(scratch1, src1, MemOperand(r0, 0), Condition(3));
vlgv(scratch2, src1, MemOperand(r0, 1), Condition(3));
lrvgr(scratch1, scratch1);
lrvgr(scratch2, scratch2);
vlvgp(dst, scratch2, scratch1);
// Clear scratch.
vx(scratch1, scratch1, scratch1, Condition(0), Condition(0), Condition(0));
vperm(dst, dst, scratch1, scratch2, Condition(0), Condition(0));
vx(scratch3, scratch3, scratch3, Condition(0), Condition(0), Condition(0));
vperm(dst, dst, scratch3, scratch4, Condition(0), Condition(0));
}
void TurboAssembler::I8x16Shuffle(Simd128Register dst, Simd128Register src1,
@ -6003,7 +6006,7 @@ void TurboAssembler::I8x16Shuffle(Simd128Register dst, Simd128Register src1,
Register scratch2, Simd128Register scratch3) {
mov(scratch1, Operand(low));
mov(scratch2, Operand(high));
vlvgp(kScratchDoubleReg, scratch2, scratch1);
vlvgp(scratch3, scratch2, scratch1);
vperm(dst, src1, src2, scratch3, Condition(0), Condition(0));
}
@ -6174,8 +6177,6 @@ void MacroAssembler::LoadStackLimit(Register destination, StackLimitKind kind) {
LoadU64(destination, MemOperand(kRootRegister, offset));
}
#undef kScratchDoubleReg
} // namespace internal
} // namespace v8

243
src/codegen/s390/macro-assembler-s390.h
View File

@ -1102,33 +1102,43 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
void I16x8Splat(Simd128Register dst, Register src);
void I8x16Splat(Simd128Register dst, Register src);
void F64x2ExtractLane(DoubleRegister dst, Simd128Register src,
uint8_t imm_lane_idx);
uint8_t imm_lane_idx, Register = r0);
void F32x4ExtractLane(DoubleRegister dst, Simd128Register src,
uint8_t imm_lane_idx);
void I64x2ExtractLane(Register dst, Simd128Register src,
uint8_t imm_lane_idx);
void I32x4ExtractLane(Register dst, Simd128Register src,
uint8_t imm_lane_idx);
uint8_t imm_lane_idx, Register = r0);
void I64x2ExtractLane(Register dst, Simd128Register src, uint8_t imm_lane_idx,
Register = r0);
void I32x4ExtractLane(Register dst, Simd128Register src, uint8_t imm_lane_idx,
Register = r0);
void I16x8ExtractLaneU(Register dst, Simd128Register src,
uint8_t imm_lane_idx);
uint8_t imm_lane_idx, Register = r0);
void I16x8ExtractLaneS(Register dst, Simd128Register src,
uint8_t imm_lane_idx);
uint8_t imm_lane_idx, Register scratch);
void I8x16ExtractLaneU(Register dst, Simd128Register src,
uint8_t imm_lane_idx);
uint8_t imm_lane_idx, Register = r0);
void I8x16ExtractLaneS(Register dst, Simd128Register src,
uint8_t imm_lane_idx);
uint8_t imm_lane_idx, Register scratch);
void F64x2ReplaceLane(Simd128Register dst, Simd128Register src1,
DoubleRegister src2, uint8_t imm_lane_idx);
DoubleRegister src2, uint8_t imm_lane_idx,
Register scratch);
void F32x4ReplaceLane(Simd128Register dst, Simd128Register src1,
DoubleRegister src2, uint8_t imm_lane_idx);
DoubleRegister src2, uint8_t imm_lane_idx,
Register scratch);
void I64x2ReplaceLane(Simd128Register dst, Simd128Register src1,
Register src2, uint8_t imm_lane_idx);
Register src2, uint8_t imm_lane_idx, Register = r0);
void I32x4ReplaceLane(Simd128Register dst, Simd128Register src1,
Register src2, uint8_t imm_lane_idx);
Register src2, uint8_t imm_lane_idx, Register = r0);
void I16x8ReplaceLane(Simd128Register dst, Simd128Register src1,
Register src2, uint8_t imm_lane_idx);
Register src2, uint8_t imm_lane_idx, Register = r0);
void I8x16ReplaceLane(Simd128Register dst, Simd128Register src1,
Register src2, uint8_t imm_lane_idx);
Register src2, uint8_t imm_lane_idx, Register = r0);
void I64x2Mul(Simd128Register dst, Simd128Register src1, Simd128Register src2,
Register scratch1, Register scratch2, Register scratch3);
void I32x4GeU(Simd128Register dst, Simd128Register src1, Simd128Register src2,
Simd128Register scratch);
void I16x8GeU(Simd128Register dst, Simd128Register src1, Simd128Register src2,
Simd128Register scratch);
void I8x16GeU(Simd128Register dst, Simd128Register src1, Simd128Register src2,
Simd128Register scratch);
void I64x2BitMask(Register dst, Simd128Register src, Register scratch1,
Simd128Register scratch2);
void I32x4BitMask(Register dst, Simd128Register src, Register scratch1,
@ -1165,8 +1175,8 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
void I32x4TruncSatF64x2UZero(Simd128Register dst, Simd128Register src,
Simd128Register scratch);
void I8x16Swizzle(Simd128Register dst, Simd128Register src1,
Simd128Register src2, Simd128Register scratch1,
Simd128Register scratch2);
Simd128Register src2, Register scratch1, Register scratch2,
Simd128Register scratch3, Simd128Register scratch4);
void S128Const(Simd128Register dst, uint64_t high, uint64_t low,
Register scratch1, Register scratch2);
void I8x16Shuffle(Simd128Register dst, Simd128Register src1,
@ -1181,6 +1191,29 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
void S128Select(Simd128Register dst, Simd128Register src1,
Simd128Register src2, Simd128Register mask);
#define SIMD_SHIFT_LIST(V) \
V(I64x2Shl) \
V(I64x2ShrS) \
V(I64x2ShrU) \
V(I32x4Shl) \
V(I32x4ShrS) \
V(I32x4ShrU) \
V(I16x8Shl) \
V(I16x8ShrS) \
V(I16x8ShrU) \
V(I8x16Shl) \
V(I8x16ShrS) \
V(I8x16ShrU)
#define PROTOTYPE_SIMD_SHIFT(name) \
void name(Simd128Register dst, Simd128Register src1, Register src2, \
Simd128Register scratch); \
void name(Simd128Register dst, Simd128Register src1, const Operand& src2, \
Register scratch1, Simd128Register scratch2);
SIMD_SHIFT_LIST(PROTOTYPE_SIMD_SHIFT)
#undef PROTOTYPE_SIMD_SHIFT
#undef SIMD_SHIFT_LIST
#define SIMD_UNOP_LIST(V) \
V(F64x2Abs) \
V(F64x2Neg) \
@ -1230,108 +1263,80 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
#undef SIMD_UNOP_LIST
#define SIMD_BINOP_LIST(V) \
V(F64x2Add, Simd128Register) \
V(F64x2Sub, Simd128Register) \
V(F64x2Mul, Simd128Register) \
V(F64x2Div, Simd128Register) \
V(F64x2Min, Simd128Register) \
V(F64x2Max, Simd128Register) \
V(F64x2Eq, Simd128Register) \
V(F64x2Ne, Simd128Register) \
V(F64x2Lt, Simd128Register) \
V(F64x2Le, Simd128Register) \
V(F64x2Pmin, Simd128Register) \
V(F64x2Pmax, Simd128Register) \
V(F32x4Add, Simd128Register) \
V(F32x4Sub, Simd128Register) \
V(F32x4Mul, Simd128Register) \
V(F32x4Div, Simd128Register) \
V(F32x4Min, Simd128Register) \
V(F32x4Max, Simd128Register) \
V(F32x4Eq, Simd128Register) \
V(F32x4Ne, Simd128Register) \
V(F32x4Lt, Simd128Register) \
V(F32x4Le, Simd128Register) \
V(F32x4Pmin, Simd128Register) \
V(F32x4Pmax, Simd128Register) \
V(I64x2Add, Simd128Register) \
V(I64x2Sub, Simd128Register) \
V(I64x2Mul, Simd128Register) \
V(I64x2Eq, Simd128Register) \
V(I64x2Ne, Simd128Register) \
V(I64x2GtS, Simd128Register) \
V(I64x2GeS, Simd128Register) \
V(I64x2Shl, Register) \
V(I64x2ShrS, Register) \
V(I64x2ShrU, Register) \
V(I64x2Shl, const Operand&) \
V(I64x2ShrS, const Operand&) \
V(I64x2ShrU, const Operand&) \
V(I32x4Add, Simd128Register) \
V(I32x4Sub, Simd128Register) \
V(I32x4Mul, Simd128Register) \
V(I32x4Eq, Simd128Register) \
V(I32x4Ne, Simd128Register) \
V(I32x4GtS, Simd128Register) \
V(I32x4GeS, Simd128Register) \
V(I32x4GtU, Simd128Register) \
V(I32x4GeU, Simd128Register) \
V(I32x4MinS, Simd128Register) \
V(I32x4MinU, Simd128Register) \
V(I32x4MaxS, Simd128Register) \
V(I32x4MaxU, Simd128Register) \
V(I32x4Shl, Register) \
V(I32x4ShrS, Register) \
V(I32x4ShrU, Register) \
V(I32x4Shl, const Operand&) \
V(I32x4ShrS, const Operand&) \
V(I32x4ShrU, const Operand&) \
V(I16x8Add, Simd128Register) \
V(I16x8Sub, Simd128Register) \
V(I16x8Mul, Simd128Register) \
V(I16x8Eq, Simd128Register) \
V(I16x8Ne, Simd128Register) \
V(I16x8GtS, Simd128Register) \
V(I16x8GeS, Simd128Register) \
V(I16x8GtU, Simd128Register) \
V(I16x8GeU, Simd128Register) \
V(I16x8MinS, Simd128Register) \
V(I16x8MinU, Simd128Register) \
V(I16x8MaxS, Simd128Register) \
V(I16x8MaxU, Simd128Register) \
V(I16x8Shl, Register) \
V(I16x8ShrS, Register) \
V(I16x8ShrU, Register) \
V(I16x8Shl, const Operand&) \
V(I16x8ShrS, const Operand&) \
V(I16x8ShrU, const Operand&) \
V(I16x8RoundingAverageU, Simd128Register) \
V(I8x16Add, Simd128Register) \
V(I8x16Sub, Simd128Register) \
V(I8x16Eq, Simd128Register) \
V(I8x16Ne, Simd128Register) \
V(I8x16GtS, Simd128Register) \
V(I8x16GeS, Simd128Register) \
V(I8x16GtU, Simd128Register) \
V(I8x16GeU, Simd128Register) \
V(I8x16MinS, Simd128Register) \
V(I8x16MinU, Simd128Register) \
V(I8x16MaxS, Simd128Register) \
V(I8x16MaxU, Simd128Register) \
V(I8x16Shl, Register) \
V(I8x16ShrS, Register) \
V(I8x16ShrU, Register) \
V(I8x16Shl, const Operand&) \
V(I8x16ShrS, const Operand&) \
V(I8x16ShrU, const Operand&) \
V(I8x16RoundingAverageU, Simd128Register) \
V(S128And, Simd128Register) \
V(S128Or, Simd128Register) \
V(S128Xor, Simd128Register) \
V(S128AndNot, Simd128Register)
V(F64x2Add) \
V(F64x2Sub) \
V(F64x2Mul) \
V(F64x2Div) \
V(F64x2Min) \
V(F64x2Max) \
V(F64x2Eq) \
V(F64x2Ne) \
V(F64x2Lt) \
V(F64x2Le) \
V(F64x2Pmin) \
V(F64x2Pmax) \
V(F32x4Add) \
V(F32x4Sub) \
V(F32x4Mul) \
V(F32x4Div) \
V(F32x4Min) \
V(F32x4Max) \
V(F32x4Eq) \
V(F32x4Ne) \
V(F32x4Lt) \
V(F32x4Le) \
V(F32x4Pmin) \
V(F32x4Pmax) \
V(I64x2Add) \
V(I64x2Sub) \
V(I64x2Eq) \
V(I64x2Ne) \
V(I64x2GtS) \
V(I64x2GeS) \
V(I32x4Add) \
V(I32x4Sub) \
V(I32x4Mul) \
V(I32x4Eq) \
V(I32x4Ne) \
V(I32x4GtS) \
V(I32x4GeS) \
V(I32x4GtU) \
V(I32x4MinS) \
V(I32x4MinU) \
V(I32x4MaxS) \
V(I32x4MaxU) \
V(I16x8Add) \
V(I16x8Sub) \
V(I16x8Mul) \
V(I16x8Eq) \
V(I16x8Ne) \
V(I16x8GtS) \
V(I16x8GeS) \
V(I16x8GtU) \
V(I16x8MinS) \
V(I16x8MinU) \
V(I16x8MaxS) \
V(I16x8MaxU) \
V(I16x8RoundingAverageU) \
V(I8x16Add) \
V(I8x16Sub) \
V(I8x16Eq) \
V(I8x16Ne) \
V(I8x16GtS) \
V(I8x16GeS) \
V(I8x16GtU) \
V(I8x16MinS) \
V(I8x16MinU) \
V(I8x16MaxS) \
V(I8x16MaxU) \
V(I8x16RoundingAverageU) \
V(S128And) \
V(S128Or) \
V(S128Xor) \
V(S128AndNot)
#define PROTOTYPE_SIMD_BINOP(name, stype) \
void name(Simd128Register dst, Simd128Register src1, stype src2);
#define PROTOTYPE_SIMD_BINOP(name) \
void name(Simd128Register dst, Simd128Register src1, Simd128Register src2);
SIMD_BINOP_LIST(PROTOTYPE_SIMD_BINOP)
#undef PROTOTYPE_SIMD_BINOP
#undef SIMD_BINOP_LIST

215
src/compiler/backend/s390/code-generator-s390.cc
View File

@ -2556,99 +2556,107 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
ASSEMBLE_ATOMIC64_COMP_EXCHANGE_WORD64();
break;
// Simd Support.
#define SIMD_BINOP_LIST(V) \
V(F64x2Add, Simd128Register) \
V(F64x2Sub, Simd128Register) \
V(F64x2Mul, Simd128Register) \
V(F64x2Div, Simd128Register) \
V(F64x2Min, Simd128Register) \
V(F64x2Max, Simd128Register) \
V(F64x2Eq, Simd128Register) \
V(F64x2Ne, Simd128Register) \
V(F64x2Lt, Simd128Register) \
V(F64x2Le, Simd128Register) \
V(F64x2Pmin, Simd128Register) \
V(F64x2Pmax, Simd128Register) \
V(F32x4Add, Simd128Register) \
V(F32x4Sub, Simd128Register) \
V(F32x4Mul, Simd128Register) \
V(F32x4Div, Simd128Register) \
V(F32x4Min, Simd128Register) \
V(F32x4Max, Simd128Register) \
V(F32x4Eq, Simd128Register) \
V(F32x4Ne, Simd128Register) \
V(F32x4Lt, Simd128Register) \
V(F32x4Le, Simd128Register) \
V(F32x4Pmin, Simd128Register) \
V(F32x4Pmax, Simd128Register) \
V(I64x2Add, Simd128Register) \
V(I64x2Sub, Simd128Register) \
V(I64x2Mul, Simd128Register) \
V(I64x2Eq, Simd128Register) \
V(I64x2Ne, Simd128Register) \
V(I64x2GtS, Simd128Register) \
V(I64x2GeS, Simd128Register) \
V(I64x2Shl, Register) \
V(I64x2ShrS, Register) \
V(I64x2ShrU, Register) \
V(I32x4Add, Simd128Register) \
V(I32x4Sub, Simd128Register) \
V(I32x4Mul, Simd128Register) \
V(I32x4Eq, Simd128Register) \
V(I32x4Ne, Simd128Register) \
V(I32x4GtS, Simd128Register) \
V(I32x4GeS, Simd128Register) \
V(I32x4GtU, Simd128Register) \
V(I32x4GeU, Simd128Register) \
V(I32x4MinS, Simd128Register) \
V(I32x4MinU, Simd128Register) \
V(I32x4MaxS, Simd128Register) \
V(I32x4MaxU, Simd128Register) \
V(I32x4Shl, Register) \
V(I32x4ShrS, Register) \
V(I32x4ShrU, Register) \
V(I16x8Add, Simd128Register) \
V(I16x8Sub, Simd128Register) \
V(I16x8Mul, Simd128Register) \
V(I16x8Eq, Simd128Register) \
V(I16x8Ne, Simd128Register) \
V(I16x8GtS, Simd128Register) \
V(I16x8GeS, Simd128Register) \
V(I16x8GtU, Simd128Register) \
V(I16x8GeU, Simd128Register) \
V(I16x8MinS, Simd128Register) \
V(I16x8MinU, Simd128Register) \
V(I16x8MaxS, Simd128Register) \
V(I16x8MaxU, Simd128Register) \
V(I16x8Shl, Register) \
V(I16x8ShrS, Register) \
V(I16x8ShrU, Register) \
V(I16x8RoundingAverageU, Simd128Register) \
V(I8x16Add, Simd128Register) \
V(I8x16Sub, Simd128Register) \
V(I8x16Eq, Simd128Register) \
V(I8x16Ne, Simd128Register) \
V(I8x16GtS, Simd128Register) \
V(I8x16GeS, Simd128Register) \
V(I8x16GtU, Simd128Register) \
V(I8x16GeU, Simd128Register) \
V(I8x16MinS, Simd128Register) \
V(I8x16MinU, Simd128Register) \
V(I8x16MaxS, Simd128Register) \
V(I8x16MaxU, Simd128Register) \
V(I8x16Shl, Register) \
V(I8x16ShrS, Register) \
V(I8x16ShrU, Register) \
V(I8x16RoundingAverageU, Simd128Register) \
V(S128And, Simd128Register) \
V(S128Or, Simd128Register) \
V(S128Xor, Simd128Register) \
V(S128AndNot, Simd128Register)
#define SIMD_SHIFT_LIST(V) \
V(I64x2Shl) \
V(I64x2ShrS) \
V(I64x2ShrU) \
V(I32x4Shl) \
V(I32x4ShrS) \
V(I32x4ShrU) \
V(I16x8Shl) \
V(I16x8ShrS) \
V(I16x8ShrU) \
V(I8x16Shl) \
V(I8x16ShrS) \
V(I8x16ShrU)
#define EMIT_SIMD_BINOP(name, stype) \
#define EMIT_SIMD_SHIFT(name) \
case kS390_##name: { \
__ name(i.OutputSimd128Register(), i.InputSimd128Register(0), \
i.Input##stype(1)); \
i.InputRegister(1), kScratchDoubleReg); \
break; \
}
SIMD_SHIFT_LIST(EMIT_SIMD_SHIFT)
#undef EMIT_SIMD_SHIFT
#undef SIMD_SHIFT_LIST
#define SIMD_BINOP_LIST(V) \
V(F64x2Add) \
V(F64x2Sub) \
V(F64x2Mul) \
V(F64x2Div) \
V(F64x2Min) \
V(F64x2Max) \
V(F64x2Eq) \
V(F64x2Ne) \
V(F64x2Lt) \
V(F64x2Le) \
V(F64x2Pmin) \
V(F64x2Pmax) \
V(F32x4Add) \
V(F32x4Sub) \
V(F32x4Mul) \
V(F32x4Div) \
V(F32x4Min) \
V(F32x4Max) \
V(F32x4Eq) \
V(F32x4Ne) \
V(F32x4Lt) \
V(F32x4Le) \
V(F32x4Pmin) \
V(F32x4Pmax) \
V(I64x2Add) \
V(I64x2Sub) \
V(I64x2Eq) \
V(I64x2Ne) \
V(I64x2GtS) \
V(I64x2GeS) \
V(I32x4Add) \
V(I32x4Sub) \
V(I32x4Mul) \
V(I32x4Eq) \
V(I32x4Ne) \
V(I32x4GtS) \
V(I32x4GeS) \
V(I32x4GtU) \
V(I32x4MinS) \
V(I32x4MinU) \
V(I32x4MaxS) \
V(I32x4MaxU) \
V(I16x8Add) \
V(I16x8Sub) \
V(I16x8Mul) \
V(I16x8Eq) \
V(I16x8Ne) \
V(I16x8GtS) \
V(I16x8GeS) \
V(I16x8GtU) \
V(I16x8MinS) \
V(I16x8MinU) \
V(I16x8MaxS) \
V(I16x8MaxU) \
V(I16x8RoundingAverageU) \
V(I8x16Add) \
V(I8x16Sub) \
V(I8x16Eq) \
V(I8x16Ne) \
V(I8x16GtS) \
V(I8x16GeS) \
V(I8x16GtU) \
V(I8x16MinS) \
V(I8x16MinU) \
V(I8x16MaxS) \
V(I8x16MaxU) \
V(I8x16RoundingAverageU) \
V(S128And) \
V(S128Or) \
V(S128Xor) \
V(S128AndNot)
#define EMIT_SIMD_BINOP(name) \
case kS390_##name: { \
__ name(i.OutputSimd128Register(), i.InputSimd128Register(0), \
i.InputSimd128Register(1)); \
break; \
}
SIMD_BINOP_LIST(EMIT_SIMD_BINOP)
@ -2719,7 +2727,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
#define EMIT_SIMD_EXTRACT_LANE(name, dtype) \
case kS390_##name: { \
__ name(i.Output##dtype(), i.InputSimd128Register(0), i.InputInt8(1)); \
__ name(i.Output##dtype(), i.InputSimd128Register(0), i.InputInt8(1), \
kScratchReg); \
break; \
}
SIMD_EXTRACT_LANE_LIST(EMIT_SIMD_EXTRACT_LANE)
@ -2737,7 +2746,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
#define EMIT_SIMD_REPLACE_LANE(name, stype) \
case kS390_##name: { \
__ name(i.OutputSimd128Register(), i.InputSimd128Register(0), \
i.Input##stype(2), i.InputInt8(1)); \
i.Input##stype(2), i.InputInt8(1), kScratchReg); \
break; \
}
SIMD_REPLACE_LANE_LIST(EMIT_SIMD_REPLACE_LANE)
@ -2837,6 +2846,26 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
#undef EMIT_SIMD_EXT_ADD_PAIRWISE
#undef SIMD_EXT_ADD_PAIRWISE_LIST
case kS390_I64x2Mul: {
__ I64x2Mul(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), r0, r1, ip);
break;
}
case kS390_I32x4GeU: {
__ I32x4GeU(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), kScratchDoubleReg);
break;
}
case kS390_I16x8GeU: {
__ I16x8GeU(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), kScratchDoubleReg);
break;
}
case kS390_I8x16GeU: {
__ I8x16GeU(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), kScratchDoubleReg);
break;
}
// vector unary ops
case kS390_F32x4RecipApprox: {
__ mov(kScratchReg, Operand(1));
@ -2948,7 +2977,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kS390_I8x16Swizzle: {
__ I8x16Swizzle(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), kScratchDoubleReg,
i.InputSimd128Register(1), r0, r1, kScratchDoubleReg,
i.ToSimd128Register(instr->TempAt(0)));
break;
}

223
src/wasm/baseline/s390/liftoff-assembler-s390.h
View File

@ -2257,104 +2257,111 @@ void LiftoffAssembler::emit_smi_check(Register obj, Label* target,
}
#define SIMD_BINOP_RR_LIST(V) \
V(f64x2_add, F64x2Add, fp) \
V(f64x2_sub, F64x2Sub, fp) \
V(f64x2_mul, F64x2Mul, fp) \
V(f64x2_div, F64x2Div, fp) \
V(f64x2_min, F64x2Min, fp) \
V(f64x2_max, F64x2Max, fp) \
V(f64x2_eq, F64x2Eq, fp) \
V(f64x2_ne, F64x2Ne, fp) \
V(f64x2_lt, F64x2Lt, fp) \
V(f64x2_le, F64x2Le, fp) \
V(f64x2_pmin, F64x2Pmin, fp) \
V(f64x2_pmax, F64x2Pmax, fp) \
V(f32x4_add, F32x4Add, fp) \
V(f32x4_sub, F32x4Sub, fp) \
V(f32x4_mul, F32x4Mul, fp) \
V(f32x4_div, F32x4Div, fp) \
V(f32x4_min, F32x4Min, fp) \
V(f32x4_max, F32x4Max, fp) \
V(f32x4_eq, F32x4Eq, fp) \
V(f32x4_ne, F32x4Ne, fp) \
V(f32x4_lt, F32x4Lt, fp) \
V(f32x4_le, F32x4Le, fp) \
V(f32x4_pmin, F32x4Pmin, fp) \
V(f32x4_pmax, F32x4Pmax, fp) \
V(i64x2_add, I64x2Add, fp) \
V(i64x2_sub, I64x2Sub, fp) \
V(i64x2_mul, I64x2Mul, fp) \
V(i64x2_eq, I64x2Eq, fp) \
V(i64x2_ne, I64x2Ne, fp) \
V(i64x2_gt_s, I64x2GtS, fp) \
V(i64x2_ge_s, I64x2GeS, fp) \
V(i64x2_shl, I64x2Shl, gp) \
V(i64x2_shr_s, I64x2ShrS, gp) \
V(i64x2_shr_u, I64x2ShrU, gp) \
V(i32x4_add, I32x4Add, fp) \
V(i32x4_sub, I32x4Sub, fp) \
V(i32x4_mul, I32x4Mul, fp) \
V(i32x4_eq, I32x4Eq, fp) \
V(i32x4_ne, I32x4Ne, fp) \
V(i32x4_gt_s, I32x4GtS, fp) \
V(i32x4_ge_s, I32x4GeS, fp) \
V(i32x4_gt_u, I32x4GtU, fp) \
V(i32x4_ge_u, I32x4GeU, fp) \
V(i32x4_min_s, I32x4MinS, fp) \
V(i32x4_min_u, I32x4MinU, fp) \
V(i32x4_max_s, I32x4MaxS, fp) \
V(i32x4_max_u, I32x4MaxU, fp) \
V(i32x4_shl, I32x4Shl, gp) \
V(i32x4_shr_s, I32x4ShrS, gp) \
V(i32x4_shr_u, I32x4ShrU, gp) \
V(i16x8_add, I16x8Add, fp) \
V(i16x8_sub, I16x8Sub, fp) \
V(i16x8_mul, I16x8Mul, fp) \
V(i16x8_eq, I16x8Eq, fp) \
V(i16x8_ne, I16x8Ne, fp) \
V(i16x8_gt_s, I16x8GtS, fp) \
V(i16x8_ge_s, I16x8GeS, fp) \
V(i16x8_gt_u, I16x8GtU, fp) \
V(i16x8_ge_u, I16x8GeU, fp) \
V(i16x8_min_s, I16x8MinS, fp) \
V(i16x8_min_u, I16x8MinU, fp) \
V(i16x8_max_s, I16x8MaxS, fp) \
V(i16x8_max_u, I16x8MaxU, fp) \
V(i16x8_shl, I16x8Shl, gp) \
V(i16x8_shr_s, I16x8ShrS, gp) \
V(i16x8_shr_u, I16x8ShrU, gp) \
V(i16x8_rounding_average_u, I16x8RoundingAverageU, fp) \
V(i8x16_add, I8x16Add, fp) \
V(i8x16_sub, I8x16Sub, fp) \
V(i8x16_eq, I8x16Eq, fp) \
V(i8x16_ne, I8x16Ne, fp) \
V(i8x16_gt_s, I8x16GtS, fp) \
V(i8x16_ge_s, I8x16GeS, fp) \
V(i8x16_gt_u, I8x16GtU, fp) \
V(i8x16_ge_u, I8x16GeU, fp) \
V(i8x16_min_s, I8x16MinS, fp) \
V(i8x16_min_u, I8x16MinU, fp) \
V(i8x16_max_s, I8x16MaxS, fp) \
V(i8x16_max_u, I8x16MaxU, fp) \
V(i8x16_shl, I8x16Shl, gp) \
V(i8x16_shr_s, I8x16ShrS, gp) \
V(i8x16_shr_u, I8x16ShrU, gp) \
V(i8x16_rounding_average_u, I8x16RoundingAverageU, fp) \
V(s128_and, S128And, fp) \
V(s128_or, S128Or, fp) \
V(s128_xor, S128Xor, fp) \
V(s128_and_not, S128AndNot, fp)
V(f64x2_add, F64x2Add) \
V(f64x2_sub, F64x2Sub) \
V(f64x2_mul, F64x2Mul) \
V(f64x2_div, F64x2Div) \
V(f64x2_min, F64x2Min) \
V(f64x2_max, F64x2Max) \
V(f64x2_eq, F64x2Eq) \
V(f64x2_ne, F64x2Ne) \
V(f64x2_lt, F64x2Lt) \
V(f64x2_le, F64x2Le) \
V(f64x2_pmin, F64x2Pmin) \
V(f64x2_pmax, F64x2Pmax) \
V(f32x4_add, F32x4Add) \
V(f32x4_sub, F32x4Sub) \
V(f32x4_mul, F32x4Mul) \
V(f32x4_div, F32x4Div) \
V(f32x4_min, F32x4Min) \
V(f32x4_max, F32x4Max) \
V(f32x4_eq, F32x4Eq) \
V(f32x4_ne, F32x4Ne) \
V(f32x4_lt, F32x4Lt) \
V(f32x4_le, F32x4Le) \
V(f32x4_pmin, F32x4Pmin) \
V(f32x4_pmax, F32x4Pmax) \
V(i64x2_add, I64x2Add) \
V(i64x2_sub, I64x2Sub) \
V(i64x2_eq, I64x2Eq) \
V(i64x2_ne, I64x2Ne) \
V(i64x2_gt_s, I64x2GtS) \
V(i64x2_ge_s, I64x2GeS) \
V(i32x4_add, I32x4Add) \
V(i32x4_sub, I32x4Sub) \
V(i32x4_mul, I32x4Mul) \
V(i32x4_eq, I32x4Eq) \
V(i32x4_ne, I32x4Ne) \
V(i32x4_gt_s, I32x4GtS) \
V(i32x4_ge_s, I32x4GeS) \
V(i32x4_gt_u, I32x4GtU) \
V(i32x4_min_s, I32x4MinS) \
V(i32x4_min_u, I32x4MinU) \
V(i32x4_max_s, I32x4MaxS) \
V(i32x4_max_u, I32x4MaxU) \
V(i16x8_add, I16x8Add) \
V(i16x8_sub, I16x8Sub) \
V(i16x8_mul, I16x8Mul) \
V(i16x8_eq, I16x8Eq) \
V(i16x8_ne, I16x8Ne) \
V(i16x8_gt_s, I16x8GtS) \
V(i16x8_ge_s, I16x8GeS) \
V(i16x8_gt_u, I16x8GtU) \
V(i16x8_min_s, I16x8MinS) \
V(i16x8_min_u, I16x8MinU) \
V(i16x8_max_s, I16x8MaxS) \
V(i16x8_max_u, I16x8MaxU) \
V(i16x8_rounding_average_u, I16x8RoundingAverageU) \
V(i8x16_add, I8x16Add) \
V(i8x16_sub, I8x16Sub) \
V(i8x16_eq, I8x16Eq) \
V(i8x16_ne, I8x16Ne) \
V(i8x16_gt_s, I8x16GtS) \
V(i8x16_ge_s, I8x16GeS) \
V(i8x16_gt_u, I8x16GtU) \
V(i8x16_min_s, I8x16MinS) \
V(i8x16_min_u, I8x16MinU) \
V(i8x16_max_s, I8x16MaxS) \
V(i8x16_max_u, I8x16MaxU) \
V(i8x16_rounding_average_u, I8x16RoundingAverageU) \
V(s128_and, S128And) \
V(s128_or, S128Or) \
V(s128_xor, S128Xor) \
V(s128_and_not, S128AndNot)
#define EMIT_SIMD_BINOP_RR(name, op, stype) \
#define EMIT_SIMD_BINOP_RR(name, op) \
void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister lhs, \
LiftoffRegister rhs) { \
op(dst.fp(), lhs.fp(), rhs.stype()); \
op(dst.fp(), lhs.fp(), rhs.fp()); \
}
SIMD_BINOP_RR_LIST(EMIT_SIMD_BINOP_RR)
#undef EMIT_SIMD_BINOP_RR
#undef SIMD_BINOP_RR_LIST
#define SIMD_BINOP_RI_LIST(V) \
#define SIMD_SHIFT_RR_LIST(V) \
V(i64x2_shl, I64x2Shl) \
V(i64x2_shr_s, I64x2ShrS) \
V(i64x2_shr_u, I64x2ShrU) \
V(i32x4_shl, I32x4Shl) \
V(i32x4_shr_s, I32x4ShrS) \
V(i32x4_shr_u, I32x4ShrU) \
V(i16x8_shl, I16x8Shl) \
V(i16x8_shr_s, I16x8ShrS) \
V(i16x8_shr_u, I16x8ShrU) \
V(i8x16_shl, I8x16Shl) \
V(i8x16_shr_s, I8x16ShrS) \
V(i8x16_shr_u, I8x16ShrU)
#define EMIT_SIMD_SHIFT_RR(name, op) \
void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister lhs, \
LiftoffRegister rhs) { \
op(dst.fp(), lhs.fp(), rhs.gp(), kScratchDoubleReg); \
}
SIMD_SHIFT_RR_LIST(EMIT_SIMD_SHIFT_RR)
#undef EMIT_SIMD_SHIFT_RR
#undef SIMD_SHIFT_RR_LIST
#define SIMD_SHIFT_RI_LIST(V) \
V(i64x2_shli, I64x2Shl) \
V(i64x2_shri_s, I64x2ShrS) \
V(i64x2_shri_u, I64x2ShrU) \
@ -2368,14 +2375,14 @@ SIMD_BINOP_RR_LIST(EMIT_SIMD_BINOP_RR)
V(i8x16_shri_s, I8x16ShrS) \
V(i8x16_shri_u, I8x16ShrU)
#define EMIT_SIMD_BINOP_RI(name, op) \
#define EMIT_SIMD_SHIFT_RI(name, op) \
void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister lhs, \
int32_t rhs) { \
op(dst.fp(), lhs.fp(), Operand(rhs)); \
op(dst.fp(), lhs.fp(), Operand(rhs), r0, kScratchDoubleReg); \
}
SIMD_BINOP_RI_LIST(EMIT_SIMD_BINOP_RI)
#undef EMIT_SIMD_BINOP_RI
#undef SIMD_BINOP_RI_LIST
SIMD_SHIFT_RI_LIST(EMIT_SIMD_SHIFT_RI)
#undef EMIT_SIMD_SHIFT_RI
#undef SIMD_SHIFT_RI_LIST
#define SIMD_UNOP_LIST(V) \
V(f64x2_splat, F64x2Splat, fp, fp, , void) \
@ -2443,7 +2450,7 @@ SIMD_UNOP_LIST(EMIT_SIMD_UNOP)
#define EMIT_SIMD_EXTRACT_LANE(name, op, dtype) \
void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister src, \
uint8_t imm_lane_idx) { \
op(dst.dtype(), src.fp(), imm_lane_idx); \
op(dst.dtype(), src.fp(), imm_lane_idx, r0); \
}
SIMD_EXTRACT_LANE_LIST(EMIT_SIMD_EXTRACT_LANE)
#undef EMIT_SIMD_EXTRACT_LANE
@ -2461,7 +2468,7 @@ SIMD_EXTRACT_LANE_LIST(EMIT_SIMD_EXTRACT_LANE)
void LiftoffAssembler::emit_##name( \
LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, \
uint8_t imm_lane_idx) { \
op(dst.fp(), src1.fp(), src2.stype(), imm_lane_idx); \
op(dst.fp(), src1.fp(), src2.stype(), imm_lane_idx, r0); \
}
SIMD_REPLACE_LANE_LIST(EMIT_SIMD_REPLACE_LANE)
#undef EMIT_SIMD_REPLACE_LANE
@ -2682,6 +2689,26 @@ void LiftoffAssembler::StoreLane(Register dst, Register offset,
}
}
void LiftoffAssembler::emit_i64x2_mul(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
I64x2Mul(dst.fp(), lhs.fp(), rhs.fp(), r0, r1, ip);
}
void LiftoffAssembler::emit_i32x4_ge_u(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
I32x4GeU(dst.fp(), lhs.fp(), rhs.fp(), kScratchDoubleReg);
}
void LiftoffAssembler::emit_i16x8_ge_u(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
I16x8GeU(dst.fp(), lhs.fp(), rhs.fp(), kScratchDoubleReg);
}
void LiftoffAssembler::emit_i8x16_ge_u(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
I8x16GeU(dst.fp(), lhs.fp(), rhs.fp(), kScratchDoubleReg);
}
void LiftoffAssembler::emit_i8x16_swizzle(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
@ -2690,7 +2717,7 @@ void LiftoffAssembler::emit_i8x16_swizzle(LiftoffRegister dst,
Simd128Register dest = dst.fp();
Simd128Register temp =
GetUnusedRegister(kFpReg, LiftoffRegList::ForRegs(dest, src1, src2)).fp();
I8x16Swizzle(dest, src1, src2, kScratchDoubleReg, temp);
I8x16Swizzle(dest, src1, src2, r0, r1, kScratchDoubleReg, temp);
}
void LiftoffAssembler::emit_f64x2_convert_low_i32x4_s(LiftoffRegister dst,