AuroraMiddleware/v8
1
0
Fork 0
Code Issues 2 Pull Requests Releases Wiki Activity

[compiler] Fix another SIMD register spilling issue

Browse Source 
Spilling was already fixed if a fixed SIMD register overlaps with an
allocated FP register, but the other way around was missing: If an odd
FP register (in this case d1) is used as a fixed output register, but
this register is in use as the upper half of a SIMD register (in this
case q0), we did not detect this and would just use overwrite the SIMD
half.
This CL also fixes this case.

R=thibaudm@chromium.org

Bug: v8:12330, chromium:1284980
Change-Id: Id3f98b7accd77e38ab4cd5ff8910aaf5ad96a1ed
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3372910
Reviewed-by: Thibaud Michaud <thibaudm@chromium.org>
Commit-Queue: Clemens Backes <clemensb@chromium.org>
Cr-Commit-Position: refs/heads/main@{#78514}
This commit is contained in:
Clemens Backes 2022-01-07 16:07:25 +01:00 committed by V8 LUCI CQ
parent 3170b9903d
commit 1b3d232321
2 changed files with 53 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/compiler/backend/mid-tier-register-allocator.cc
View File

@ -2569,7 +2569,21 @@ void SinglePassRegisterAllocator::ReserveFixedRegister(
// Also potentially spill the "sibling SIMD register" on architectures where a
// SIMD register aliases two FP registers.
if (!kSimpleFPAliasing && rep == MachineRepresentation::kSimd128) {
if (!IsFreeOrSameVirtualRegister(reg.simdSibling(), virtual_register) &&
if (register_state()->IsAllocated(reg.simdSibling()) &&
!DefinedAfter(virtual_register, instr_index, pos)) {
SpillRegister(reg.simdSibling());
}
}
// Similarly (but the other way around), spill a SIMD register that (partly)
// overlaps with a fixed FP register. If {reg} is the lower half (i.e. an even
// register index), this is already checked above, so we only check if {reg}
// is the upper half.
if (!kSimpleFPAliasing && (reg.ToInt() & 1)) {
DCHECK_NE(MachineRepresentation::kSimd128, rep);
int allocated_vreg = VirtualRegisterForRegister(reg.simdSibling());
if (allocated_vreg != InstructionOperand::kInvalidVirtualRegister &&
VirtualRegisterDataFor(allocated_vreg).rep() ==
MachineRepresentation::kSimd128 &&
!DefinedAfter(virtual_register, instr_index, pos)) {
SpillRegister(reg.simdSibling());
}

38
test/mjsunit/regress/wasm/regress-1284980.js Normal file
View File

@ -0,0 +1,38 @@
// Copyright 2022 the V8 project authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
// Flags: --no-liftoff --turbo-force-mid-tier-regalloc
d8.file.execute('test/mjsunit/wasm/wasm-module-builder.js');
const builder = new WasmModuleBuilder();
builder.addMemory(16, 32, false);
builder.addType(makeSig([kWasmI32, kWasmI32, kWasmI32], []));
builder.addType(makeSig([kWasmS128], []));
builder.addType(makeSig([], [kWasmF64, kWasmF64]));
builder.addTag(makeSig([], []));
// Generate function 1 (out of 3).
builder.addFunction(undefined, 0 /* sig */)
.addLocals(kWasmI32, 2).addLocals(kWasmF32, 1).addLocals(kWasmI32, 1).addLocals(kWasmF64, 1)
.addBody([
kExprTry, kWasmVoid, // try i32
kExprCallFunction, 2, // call function #2
kExprI32Const, 0, // i32.const
kExprSelect, // select
kExprI32SConvertF64, // i32.trunc_f64_s
kExprI32Const, 0x00, // i32.const
kSimdPrefix, kExprI8x16Splat, // i8x16.splat
kSimdPrefix, kExprS128Store8Lane, 0x00, 0x00, 0x00, // s128.store8_lane
kExprCatch, 0, // catch
kExprCatchAll, // catch-all
kExprEnd, // end
kExprI32Const, 0x00, // i32.const
kSimdPrefix, kExprI8x16Splat, // i8x16.splat
kExprCallFunction, 1, // call function #1
]);
// Generate function 2 (out of 3).
builder.addFunction(undefined, 1 /* sig */).addBody([kExprUnreachable]);
// Generate function 3 (out of 3).
builder.addFunction(undefined, 2 /* sig */).addBody([kExprUnreachable]);
builder.toModule();