AuroraMiddleware/v8
1
0
Fork 0
Code Issues 2 Pull Requests Releases Wiki Activity

Delete unused macro, add missing undefs

Browse Source 
Change-Id: Icfacb59e7c90ee696fd7242f4441cfb2965f490b
Reviewed-on: https://chromium-review.googlesource.com/924626
Reviewed-by: Bill Budge <bbudge@chromium.org>
Reviewed-by: Ben Titzer <titzer@chromium.org>
Reviewed-by: Jaroslav Sevcik <jarin@chromium.org>
Commit-Queue: Deepti Gandluri <gdeepti@chromium.org>
Cr-Commit-Position: refs/heads/master@{#51386}
This commit is contained in:
Deepti Gandluri 2018-02-16 15:06:24 -08:00 committed by Commit Bot
parent dcd31ef223
commit 1c71991ab6
6 changed files with 38 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/compiler/arm/instruction-selector-arm.cc
View File

@ -1404,6 +1404,7 @@ void InstructionSelector::VisitUint32Mod(Node* node) {
}
RR_OP_LIST(RR_VISITOR)
#undef RR_VISITOR
#undef RR_OP_LIST
#define RR_VISITOR_V8(Name, opcode) \
void InstructionSelector::Visit##Name(Node* node) { \
@ -1412,6 +1413,7 @@ RR_OP_LIST(RR_VISITOR)
}
RR_OP_LIST_V8(RR_VISITOR_V8)
#undef RR_VISITOR_V8
#undef RR_OP_LIST_V8
#define RRR_VISITOR(Name, opcode) \
void InstructionSelector::Visit##Name(Node* node) { \
@ -1419,6 +1421,7 @@ RR_OP_LIST_V8(RR_VISITOR_V8)
}
RRR_OP_LIST(RRR_VISITOR)
#undef RRR_VISITOR
#undef RRR_OP_LIST
void InstructionSelector::VisitFloat32Add(Node* node) {
ArmOperandGenerator g(this);
@ -2299,11 +2302,6 @@ VISIT_ATOMIC_BINOP(Xor)
V(I16x8) \
V(I8x16)
#define SIMD_FORMAT_LIST(V) \
V(32x4, 4) \
V(16x8, 8) \
V(8x16, 16)
#define SIMD_UNOP_LIST(V) \
V(F32x4SConvertI32x4, kArmF32x4SConvertI32x4) \
V(F32x4UConvertI32x4, kArmF32x4UConvertI32x4) \
@ -2436,6 +2434,7 @@ SIMD_TYPE_LIST(SIMD_VISIT_EXTRACT_LANE)
}
SIMD_TYPE_LIST(SIMD_VISIT_REPLACE_LANE)
#undef SIMD_VISIT_REPLACE_LANE
#undef SIMD_TYPE_LIST
#define SIMD_VISIT_UNOP(Name, instruction) \
void InstructionSelector::Visit##Name(Node* node) { \
@ -2443,6 +2442,7 @@ SIMD_TYPE_LIST(SIMD_VISIT_REPLACE_LANE)
}
SIMD_UNOP_LIST(SIMD_VISIT_UNOP)
#undef SIMD_VISIT_UNOP
#undef SIMD_UNOP_LIST
#define SIMD_VISIT_SHIFT_OP(Name) \
void InstructionSelector::Visit##Name(Node* node) { \
@ -2450,6 +2450,7 @@ SIMD_UNOP_LIST(SIMD_VISIT_UNOP)
}
SIMD_SHIFT_OP_LIST(SIMD_VISIT_SHIFT_OP)
#undef SIMD_VISIT_SHIFT_OP
#undef SIMD_SHIFT_OP_LIST
#define SIMD_VISIT_BINOP(Name, instruction) \
void InstructionSelector::Visit##Name(Node* node) { \
@ -2457,6 +2458,7 @@ SIMD_SHIFT_OP_LIST(SIMD_VISIT_SHIFT_OP)
}
SIMD_BINOP_LIST(SIMD_VISIT_BINOP)
#undef SIMD_VISIT_BINOP
#undef SIMD_BINOP_LIST
void InstructionSelector::VisitS128Select(Node* node) {
ArmOperandGenerator g(this);

11
src/compiler/arm64/instruction-selector-arm64.cc
View File

@ -1245,6 +1245,7 @@ void InstructionSelector::VisitWord64Ror(Node* node) {
}
RR_OP_LIST(RR_VISITOR)
#undef RR_VISITOR
#undef RR_OP_LIST
#define RRR_VISITOR(Name, opcode) \
void InstructionSelector::Visit##Name(Node* node) { \
@ -1252,6 +1253,7 @@ RR_OP_LIST(RR_VISITOR)
}
RRR_OP_LIST(RRR_VISITOR)
#undef RRR_VISITOR
#undef RRR_OP_LIST
void InstructionSelector::VisitWord32Ctz(Node* node) { UNREACHABLE(); }
@ -2794,11 +2796,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I16x8) \
V(I8x16)
#define SIMD_FORMAT_LIST(V) \
V(32x4, 4) \
V(16x8, 8) \
V(8x16, 16)
#define SIMD_UNOP_LIST(V) \
V(F32x4SConvertI32x4, kArm64F32x4SConvertI32x4) \
V(F32x4UConvertI32x4, kArm64F32x4UConvertI32x4) \
@ -2931,6 +2928,7 @@ SIMD_TYPE_LIST(SIMD_VISIT_EXTRACT_LANE)
}
SIMD_TYPE_LIST(SIMD_VISIT_REPLACE_LANE)
#undef SIMD_VISIT_REPLACE_LANE
#undef SIMD_TYPE_LIST
#define SIMD_VISIT_UNOP(Name, instruction) \
void InstructionSelector::Visit##Name(Node* node) { \
@ -2938,6 +2936,7 @@ SIMD_TYPE_LIST(SIMD_VISIT_REPLACE_LANE)
}
SIMD_UNOP_LIST(SIMD_VISIT_UNOP)
#undef SIMD_VISIT_UNOP
#undef SIMD_UNOP_LIST
#define SIMD_VISIT_SHIFT_OP(Name) \
void InstructionSelector::Visit##Name(Node* node) { \
@ -2945,6 +2944,7 @@ SIMD_UNOP_LIST(SIMD_VISIT_UNOP)
}
SIMD_SHIFT_OP_LIST(SIMD_VISIT_SHIFT_OP)
#undef SIMD_VISIT_SHIFT_OP
#undef SIMD_SHIFT_OP_LIST
#define SIMD_VISIT_BINOP(Name, instruction) \
void InstructionSelector::Visit##Name(Node* node) { \
@ -2952,6 +2952,7 @@ SIMD_SHIFT_OP_LIST(SIMD_VISIT_SHIFT_OP)
}
SIMD_BINOP_LIST(SIMD_VISIT_BINOP)
#undef SIMD_VISIT_BINOP
#undef SIMD_BINOP_LIST
void InstructionSelector::VisitS128Select(Node* node) {
Arm64OperandGenerator g(this);

12
src/compiler/code-assembler.cc
View File

@ -1601,3 +1601,15 @@ Smi* CheckObjectType(Object* value, Smi* type, String* location) {
} // namespace internal
} // namespace v8
#undef REPEAT_1_TO_2
#undef REPEAT_1_TO_3
#undef REPEAT_1_TO_4
#undef REPEAT_1_TO_5
#undef REPEAT_1_TO_6
#undef REPEAT_1_TO_7
#undef REPEAT_1_TO_8
#undef REPEAT_1_TO_9
#undef REPEAT_1_TO_10
#undef REPEAT_1_TO_11
#undef REPEAT_1_TO_12

6
src/compiler/mips/instruction-selector-mips.cc
View File

@ -1966,11 +1966,6 @@ void InstructionSelector::VisitSpeculationFence(Node* node) { UNREACHABLE(); }
V(I16x8) \
V(I8x16)
#define SIMD_FORMAT_LIST(V) \
V(32x4) \
V(16x8) \
V(8x16)
#define SIMD_UNOP_LIST(V) \
V(F32x4SConvertI32x4, kMipsF32x4SConvertI32x4) \
V(F32x4UConvertI32x4, kMipsF32x4UConvertI32x4) \
@ -2289,7 +2284,6 @@ bool InstructionSelector::SupportsSpeculationPoisoning() { return false; }
#undef SIMD_SHIFT_OP_LIST
#undef SIMD_UNOP_LIST
#undef SIMD_TYPE_LIST
#undef SIMD_FORMAT_LIST
#undef TRACE_UNIMPL
#undef TRACE

7
src/compiler/mips64/instruction-selector-mips64.cc
View File

@ -2629,12 +2629,6 @@ void InstructionSelector::VisitSpeculationFence(Node* node) { UNREACHABLE(); }
V(I16x8) \
V(I8x16)
// TODO(mostynb@opera.com): this is never used, remove it?
#define SIMD_FORMAT_LIST(V) \
V(32x4) \
V(16x8) \
V(8x16)
#define SIMD_UNOP_LIST(V) \
V(F32x4SConvertI32x4, kMips64F32x4SConvertI32x4) \
V(F32x4UConvertI32x4, kMips64F32x4UConvertI32x4) \
@ -2970,7 +2964,6 @@ bool InstructionSelector::SupportsSpeculationPoisoning() { return false; }
#undef SIMD_BINOP_LIST
#undef SIMD_SHIFT_OP_LIST
#undef SIMD_UNOP_LIST
#undef SIMD_FORMAT_LIST
#undef SIMD_TYPE_LIST
#undef TRACE_UNIMPL
#undef TRACE

13
src/compiler/x64/code-generator-x64.cc
View File

@ -2771,6 +2771,19 @@ Condition FlagsConditionToCondition(FlagsCondition condition) {
UNREACHABLE();
}
#undef ASSEMBLE_UNOP
#undef ASSEMBLE_BINOP
#undef ASSEMBLE_COMPARE
#undef ASSEMBLE_MULT
#undef ASSEMBLE_SHIFT
#undef ASSEMBLE_MOVX
#undef ASSEMBLE_SSE_BINOP
#undef ASSEMBLE_SSE_UNOP
#undef ASSEMBLE_AVX_BINOP
#undef ASSEMBLE_IEEE754_BINOP
#undef ASSEMBLE_IEEE754_UNOP
#undef ASSEMBLE_ATOMIC_BINOP
} // namespace
// Assembles branches after this instruction.