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[mips][wasm-simd] Implement f64x2 splat extract replace for mips

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Port f22837dbf1

R=xwafish@gmail.com

Change-Id: Iece021bb832618cac0d111639b388d94f7da7028
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1868773
Commit-Queue: Mu Tao <pamilty@gmail.com>
Auto-Submit: Mu Tao <pamilty@gmail.com>
Reviewed-by: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Jakob Gruber <jgruber@chromium.org>
Cr-Commit-Position: refs/heads/master@{#64505}
This commit is contained in:
Mu Tao 2019-10-18 16:27:41 +08:00 committed by Commit Bot
parent b5260f5351
commit 1e256fc3f6
8 changed files with 74 additions and 0 deletions
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33
src/compiler/backend/mips/code-generator-mips.cc
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@ -1983,6 +1983,39 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
ASSEMBLE_F64X2_ARITHMETIC_BINOP(fdiv_d);
break;
}
case kMipsF64x2Splat: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
Simd128Register dst = i.OutputSimd128Register();
__ FmoveLow(kScratchReg, i.InputDoubleRegister(0));
__ insert_w(dst, 0, kScratchReg);
__ insert_w(dst, 2, kScratchReg);
__ FmoveHigh(kScratchReg, i.InputDoubleRegister(0));
__ insert_w(dst, 1, kScratchReg);
__ insert_w(dst, 3, kScratchReg);
break;
}
case kMipsF64x2ExtractLane: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ copy_u_w(kScratchReg, i.InputSimd128Register(0), i.InputInt8(1) * 2);
__ FmoveLow(i.OutputDoubleRegister(), kScratchReg);
__ copy_u_w(kScratchReg, i.InputSimd128Register(0),
i.InputInt8(1) * 2 + 1);
__ FmoveHigh(i.OutputDoubleRegister(), kScratchReg);
break;
}
case kMipsF64x2ReplaceLane: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
if (src != dst) {
__ move_v(dst, src);
}
__ FmoveLow(kScratchReg, i.InputDoubleRegister(2));
__ insert_w(dst, i.InputInt8(1) * 2, kScratchReg);
__ FmoveHigh(kScratchReg, i.InputDoubleRegister(2));
__ insert_w(dst, i.InputInt8(1) * 2 + 1, kScratchReg);
break;
}
case kMipsF32x4Splat: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ FmoveLow(kScratchReg, i.InputSingleRegister(0));

3
src/compiler/backend/mips/instruction-codes-mips.h
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@ -164,6 +164,9 @@ namespace compiler {
V(MipsI32x4ShrU) \
V(MipsI32x4MaxU) \
V(MipsI32x4MinU) \
V(MipsF64x2Splat) \
V(MipsF64x2ExtractLane) \
V(MipsF64x2ReplaceLane) \
V(MipsF32x4Abs) \
V(MipsF32x4Neg) \
V(MipsF32x4Sqrt) \

3
src/compiler/backend/mips/instruction-scheduler-mips.cc
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@ -48,6 +48,9 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMipsF64x2Sub:
case kMipsF64x2Mul:
case kMipsF64x2Div:
case kMipsF64x2Splat:
case kMipsF64x2ExtractLane:
case kMipsF64x2ReplaceLane:
case kMipsF32x4Abs:
case kMipsF32x4Add:
case kMipsF32x4AddHoriz:

3
src/compiler/backend/mips/instruction-selector-mips.cc
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@ -2139,6 +2139,7 @@ void InstructionSelector::VisitS128Zero(Node* node) {
VisitRR(this, kMips##Type##Splat, node); \
}
SIMD_TYPE_LIST(SIMD_VISIT_SPLAT)
SIMD_VISIT_SPLAT(F64x2)
#undef SIMD_VISIT_SPLAT
#define SIMD_VISIT_EXTRACT_LANE(Type) \
@ -2146,6 +2147,7 @@ SIMD_TYPE_LIST(SIMD_VISIT_SPLAT)
VisitRRI(this, kMips##Type##ExtractLane, node); \
}
SIMD_TYPE_LIST(SIMD_VISIT_EXTRACT_LANE)
SIMD_VISIT_EXTRACT_LANE(F64x2)
#undef SIMD_VISIT_EXTRACT_LANE
#define SIMD_VISIT_REPLACE_LANE(Type) \
@ -2153,6 +2155,7 @@ SIMD_TYPE_LIST(SIMD_VISIT_EXTRACT_LANE)
VisitRRIR(this, kMips##Type##ReplaceLane, node); \
}
SIMD_TYPE_LIST(SIMD_VISIT_REPLACE_LANE)
SIMD_VISIT_REPLACE_LANE(F64x2)
#undef SIMD_VISIT_REPLACE_LANE
#define SIMD_VISIT_UNOP(Name, instruction) \

23
src/compiler/backend/mips64/code-generator-mips64.cc
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@ -2098,6 +2098,29 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
ASSEMBLE_F64X2_ARITHMETIC_BINOP(fdiv_d);
break;
}
case kMips64F64x2Splat: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ Move(kScratchReg, i.InputDoubleRegister(0));
__ fill_d(i.OutputSimd128Register(), kScratchReg);
break;
}
case kMips64F64x2ExtractLane: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ copy_s_d(kScratchReg, i.InputSimd128Register(0), i.InputInt8(1));
__ Move(i.OutputDoubleRegister(), kScratchReg);
break;
}
case kMips64F64x2ReplaceLane: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
if (src != dst) {
__ move_v(dst, src);
}
__ Move(kScratchReg, i.InputDoubleRegister(2));
__ insert_d(dst, i.InputInt8(1), kScratchReg);
break;
}
case kMips64F32x4Splat: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ FmoveLow(kScratchReg, i.InputSingleRegister(0));

3
src/compiler/backend/mips64/instruction-codes-mips64.h
View File

@ -194,6 +194,9 @@ namespace compiler {
V(Mips64F64x2Sub) \
V(Mips64F64x2Mul) \
V(Mips64F64x2Div) \
V(Mips64F64x2Splat) \
V(Mips64F64x2ExtractLane) \
V(Mips64F64x2ReplaceLane) \
V(Mips64F32x4Abs) \
V(Mips64F32x4Neg) \
V(Mips64F32x4Sqrt) \

3
src/compiler/backend/mips64/instruction-scheduler-mips64.cc
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@ -97,6 +97,9 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMips64F32x4Splat:
case kMips64F32x4Sub:
case kMips64F32x4UConvertI32x4:
case kMips64F64x2Splat:
case kMips64F64x2ExtractLane:
case kMips64F64x2ReplaceLane:
case kMips64Float32Max:
case kMips64Float32Min:
case kMips64Float32RoundDown:

3
src/compiler/backend/mips64/instruction-selector-mips64.cc
View File

@ -2802,6 +2802,7 @@ void InstructionSelector::VisitS128Zero(Node* node) {
VisitRR(this, kMips64##Type##Splat, node); \
}
SIMD_TYPE_LIST(SIMD_VISIT_SPLAT)
SIMD_VISIT_SPLAT(F64x2)
#undef SIMD_VISIT_SPLAT
#define SIMD_VISIT_EXTRACT_LANE(Type) \
@ -2809,6 +2810,7 @@ SIMD_TYPE_LIST(SIMD_VISIT_SPLAT)
VisitRRI(this, kMips64##Type##ExtractLane, node); \
}
SIMD_TYPE_LIST(SIMD_VISIT_EXTRACT_LANE)
SIMD_VISIT_EXTRACT_LANE(F64x2)
#undef SIMD_VISIT_EXTRACT_LANE
#define SIMD_VISIT_REPLACE_LANE(Type) \
@ -2816,6 +2818,7 @@ SIMD_TYPE_LIST(SIMD_VISIT_EXTRACT_LANE)
VisitRRIR(this, kMips64##Type##ReplaceLane, node); \
}
SIMD_TYPE_LIST(SIMD_VISIT_REPLACE_LANE)
SIMD_VISIT_REPLACE_LANE(F64x2)
#undef SIMD_VISIT_REPLACE_LANE
#define SIMD_VISIT_UNOP(Name, instruction) \