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S390 [liftoff]: initiate simd binary operations

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Starting with Simd Add ops which are ported to liftoff.

Change-Id: I2128303accf9bc47812560f5aa38b5ccfc2e3e78
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3049070
Reviewed-by: Junliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#75890}
This commit is contained in:
Milad Fa 2021-07-23 09:35:57 -04:00 committed by V8 LUCI CQ
parent 4d35ca1b9f
commit 1f79309aaa
4 changed files with 64 additions and 66 deletions
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17
src/codegen/s390/macro-assembler-s390.cc
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@ -5210,6 +5210,23 @@ void TurboAssembler::I8x16ReplaceLane(Simd128Register dst, Simd128Register src1,
vlvg(dst, src2, MemOperand(r0, 15 - imm_lane_idx), Condition(0));
}
#define SIMD_BINOP_LIST(V) \
V(F64x2Add, vfa, 3) \
V(F32x4Add, vfa, 2) \
V(I64x2Add, va, 3) \
V(I32x4Add, va, 2) \
V(I16x8Add, va, 1) \
V(I8x16Add, va, 0)
#define EMIT_SIMD_BINOP(name, op, condition) \
void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \
Simd128Register src2) { \
op(dst, src1, src2, Condition(0), Condition(0), Condition(condition)); \
}
SIMD_BINOP_LIST(EMIT_SIMD_BINOP)
#undef EMIT_SIMD_BINOP
#undef SIMD_BINOP_LIST
} // namespace internal
} // namespace v8

12
src/codegen/s390/macro-assembler-s390.h
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@ -1066,6 +1066,18 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
Register src2, uint8_t imm_lane_idx);
void I8x16ReplaceLane(Simd128Register dst, Simd128Register src1,
Register src2, uint8_t imm_lane_idx);
void F64x2Add(Simd128Register dst, Simd128Register src1,
Simd128Register src2);
void F32x4Add(Simd128Register dst, Simd128Register src1,
Simd128Register src2);
void I64x2Add(Simd128Register dst, Simd128Register src1,
Simd128Register src2);
void I32x4Add(Simd128Register dst, Simd128Register src1,
Simd128Register src2);
void I16x8Add(Simd128Register dst, Simd128Register src1,
Simd128Register src2);
void I8x16Add(Simd128Register dst, Simd128Register src1,
Simd128Register src2);
// ---------------------------------------------------------------------------
// Pointer compression Support

54
src/compiler/backend/s390/code-generator-s390.cc
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@ -2482,6 +2482,24 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
ASSEMBLE_ATOMIC64_COMP_EXCHANGE_WORD64();
break;
// Simd Support.
#define SIMD_BINOP_LIST(V) \
V(F64x2Add) \
V(F32x4Add) \
V(I64x2Add) \
V(I32x4Add) \
V(I16x8Add) \
V(I8x16Add)
#define EMIT_SIMD_BINOP(name) \
case kS390_##name: { \
__ name(i.OutputSimd128Register(), i.InputSimd128Register(0), \
i.InputSimd128Register(1)); \
break; \
}
SIMD_BINOP_LIST(EMIT_SIMD_BINOP)
#undef EMIT_SIMD_BINOP
#undef SIMD_BINOP_LIST
#define SIMD_UNOP_LIST(V) \
V(F64x2Splat, F64x2Splat, Simd128Register, DoubleRegister) \
V(F32x4Splat, F32x4Splat, Simd128Register, DoubleRegister) \
@ -2536,12 +2554,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
#undef EMIT_SIMD_REPLACE_LANE
#undef SIMD_REPLACE_LANE_LIST
// vector binops
case kS390_F64x2Add: {
__ vfa(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(3));
break;
}
case kS390_F64x2Sub: {
__ vfs(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
@ -2588,12 +2600,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ vfnms(dst, src1, src2, src0, Condition(3), Condition(0));
break;
}
case kS390_F32x4Add: {
__ vfa(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(2));
break;
}
case kS390_F32x4Sub: {
__ vfs(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
@ -2640,12 +2646,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ vfnms(dst, src1, src2, src0, Condition(2), Condition(0));
break;
}
case kS390_I64x2Add: {
__ va(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(3));
break;
}
case kS390_I64x2Sub: {
__ vs(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
@ -2667,12 +2667,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ vlvgp(i.OutputSimd128Register(), r0, r1);
break;
}
case kS390_I32x4Add: {
__ va(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(2));
break;
}
case kS390_I32x4Sub: {
__ vs(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
@ -2685,12 +2679,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Condition(2));
break;
}
case kS390_I16x8Add: {
__ va(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(1));
break;
}
case kS390_I16x8Sub: {
__ vs(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
@ -2703,12 +2691,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Condition(1));
break;
}
case kS390_I8x16Add: {
__ va(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(0));
break;
}
case kS390_I8x16Sub: {
__ vs(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),

47
src/wasm/baseline/s390/liftoff-assembler-s390.h
View File

@ -2142,6 +2142,23 @@ void LiftoffAssembler::emit_smi_check(Register obj, Label* target,
b(condition, target); // branch if SMI
}
#define SIMD_BINOP_LIST(V) \
V(f64x2_add, F64x2Add) \
V(f32x4_add, F32x4Add) \
V(i64x2_add, I64x2Add) \
V(i32x4_add, I32x4Add) \
V(i16x8_add, I16x8Add) \
V(i8x16_add, I8x16Add)
#define EMIT_SIMD_BINOP(name, op) \
void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister lhs, \
LiftoffRegister rhs) { \
op(dst.fp(), lhs.fp(), rhs.fp()); \
}
SIMD_BINOP_LIST(EMIT_SIMD_BINOP)
#undef EMIT_SIMD_BINOP
#undef SIMD_BINOP_LIST
#define SIMD_UNOP_LIST(V) \
V(f64x2_splat, F64x2Splat, fp, fp) \
V(f32x4_splat, F32x4Splat, fp, fp) \
@ -2263,11 +2280,6 @@ bool LiftoffAssembler::emit_f64x2_nearest_int(LiftoffRegister dst,
return true;
}
void LiftoffAssembler::emit_f64x2_add(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_f64x2add");
}
void LiftoffAssembler::emit_f64x2_sub(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_f64x2sub");
@ -2357,11 +2369,6 @@ bool LiftoffAssembler::emit_f32x4_nearest_int(LiftoffRegister dst,
return true;
}
void LiftoffAssembler::emit_f32x4_add(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_f32x4add");
}
void LiftoffAssembler::emit_f32x4_sub(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_f32x4sub");
@ -2439,11 +2446,6 @@ void LiftoffAssembler::emit_i64x2_shri_u(LiftoffRegister dst,
bailout(kSimd, "i64x2_shri_u");
}
void LiftoffAssembler::emit_i64x2_add(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i64x2add");
}
void LiftoffAssembler::emit_i64x2_sub(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i64x2sub");
@ -2550,11 +2552,6 @@ void LiftoffAssembler::emit_i32x4_shri_u(LiftoffRegister dst,
bailout(kSimd, "i32x4_shri_u");
}
void LiftoffAssembler::emit_i32x4_add(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i32x4add");
}
void LiftoffAssembler::emit_i32x4_sub(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i32x4sub");
@ -2676,11 +2673,6 @@ void LiftoffAssembler::emit_i16x8_shri_u(LiftoffRegister dst,
bailout(kSimd, "i16x8_shri_u");
}
void LiftoffAssembler::emit_i16x8_add(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i16x8add");
}
void LiftoffAssembler::emit_i16x8_add_sat_s(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
@ -2844,11 +2836,6 @@ void LiftoffAssembler::emit_i8x16_shri_u(LiftoffRegister dst,
bailout(kSimd, "i8x16_shri_u");
}
void LiftoffAssembler::emit_i8x16_add(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i8x16add");
}
void LiftoffAssembler::emit_i8x16_add_sat_s(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {