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[wasm-simd] Prototype prefetch for x64

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Bug: v8:11168
Change-Id: I88fd086b83bd4a17aae145fb02280a4d36b31579
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2641199
Commit-Queue: Deepti Gandluri <gdeepti@chromium.org>
Reviewed-by: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#72238}
This commit is contained in:
Deepti Gandluri 2021-01-21 11:20:14 -08:00 committed by Commit Bot
parent ae85cde159
commit 1f9fdbe3a1
8 changed files with 49 additions and 4 deletions
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10
src/codegen/x64/assembler-x64.cc
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@ -1188,6 +1188,16 @@ void Assembler::cpuid() {
emit(0xA2);
}
void Assembler::prefetch(Operand src, int level) {
DCHECK(is_uint2(level));
EnsureSpace ensure_space(this);
emit(0x0F);
emit(0x18);
// Emit hint number in Reg position of RegR/M.
XMMRegister code = XMMRegister::from_code(level);
emit_sse_operand(code, src);
}
void Assembler::cqo() {
EnsureSpace ensure_space(this);
emit_rex_64();

1
src/codegen/x64/assembler-x64.h
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@ -786,6 +786,7 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
void ret(int imm16);
void ud2();
void setcc(Condition cc, Register reg);
void prefetch(Operand src, int level);
void pblendw(XMMRegister dst, Operand src, uint8_t mask);
void pblendw(XMMRegister dst, XMMRegister src, uint8_t mask);

4
src/compiler/backend/instruction-selector.cc
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@ -2771,13 +2771,13 @@ void InstructionSelector::VisitI64x2UConvertI32x4High(Node* node) {
// && !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS64 &&
// !V8_TARGET_ARCH_MIPS
#if !V8_TARGET_ARCH_ARM64
#if !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64
// TODO(v8:11168): Prototyping prefetch.
void InstructionSelector::VisitPrefetchTemporal(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitPrefetchNonTemporal(Node* node) {
UNIMPLEMENTED();
}
#endif // !V8_TARGET_ARCH_ARM64
#endif // !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64
#if !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_X64
// TODO(v8:11002) Prototype i8x16.popcnt.

6
src/compiler/backend/x64/code-generator-x64.cc
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@ -4163,6 +4163,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
ASSEMBLE_SIMD_ALL_TRUE(Pcmpeqb);
break;
}
case kX64Prefetch:
__ prefetch(i.MemoryOperand(), 1);
break;
case kX64PrefetchNta:
__ prefetch(i.MemoryOperand(), 0);
break;
case kWord32AtomicExchangeInt8: {
__ xchgb(i.InputRegister(0), i.MemoryOperand(1));
__ movsxbl(i.InputRegister(0), i.InputRegister(0));

2
src/compiler/backend/x64/instruction-codes-x64.h
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@ -389,6 +389,8 @@ namespace compiler {
V(X64V16x8AllTrue) \
V(X64V8x16AnyTrue) \
V(X64V8x16AllTrue) \
V(X64Prefetch) \
V(X64PrefetchNta) \
V(X64Word64AtomicAddUint8) \
V(X64Word64AtomicAddUint16) \
V(X64Word64AtomicAddUint32) \

2
src/compiler/backend/x64/instruction-scheduler-x64.cc
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@ -418,6 +418,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kX64MFence:
case kX64LFence:
case kX64Prefetch:
case kX64PrefetchNta:
return kHasSideEffect;
case kX64Word64AtomicAddUint8:

24
src/compiler/backend/x64/instruction-selector-x64.cc
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@ -575,6 +575,30 @@ void InstructionSelector::VisitStoreLane(Node* node) {
Emit(opcode, 0, nullptr, input_count, inputs);
}
void InstructionSelector::VisitPrefetchTemporal(Node* node) {
X64OperandGenerator g(this);
InstructionOperand inputs[2];
size_t input_count = 0;
InstructionCode opcode = kX64Prefetch;
AddressingMode addressing_mode =
g.GetEffectiveAddressMemoryOperand(node, inputs, &input_count);
DCHECK_LE(input_count, 2);
opcode |= AddressingModeField::encode(addressing_mode);
Emit(opcode, 0, nullptr, input_count, inputs);
}
void InstructionSelector::VisitPrefetchNonTemporal(Node* node) {
X64OperandGenerator g(this);
InstructionOperand inputs[2];
size_t input_count = 0;
InstructionCode opcode = kX64PrefetchNta;
AddressingMode addressing_mode =
g.GetEffectiveAddressMemoryOperand(node, inputs, &input_count);
DCHECK_LE(input_count, 2);
opcode |= AddressingModeField::encode(addressing_mode);
Emit(opcode, 0, nullptr, input_count, inputs);
}
// Shared routine for multiple binary operations.
static void VisitBinop(InstructionSelector* selector, Node* node,
InstructionCode opcode, FlagsContinuation* cont) {

4
test/cctest/wasm/test-run-wasm-simd.cc
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@ -3805,7 +3805,7 @@ WASM_SIMD_TEST(SimdF32x4SetGlobal) {
CHECK_EQ(GetScalar(global, 3), 65.0f);
}
#if V8_TARGET_ARCH_ARM64
#if V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_X64
// TODO(v8:11168): Prototyping prefetch.
WASM_SIMD_TEST(SimdPrefetch) {
FLAG_SCOPE(wasm_simd_post_mvp);
@ -3857,7 +3857,7 @@ WASM_SIMD_TEST(SimdPrefetch) {
}
}
}
#endif // V8_TARGET_ARCH_ARM64
#endif // V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_X64
WASM_SIMD_TEST(SimdLoadStoreLoad) {
WasmRunner<int32_t> r(execution_tier, lower_simd);