Landing for Rodolph Perfetta.
Fix the ARM simulator, the ARM disassembler and extend the stop feature. The stop feature in the simulator now support enabling, disabling and counting. BUG=None TEST=None git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5723 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
This commit is contained in:
ager@chromium.org
parent
c964e478bf
commit
2122827893
@ -1004,7 +1004,7 @@ void Assembler::blx(int branch_offset) { // v5 and above
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int h = ((branch_offset & 2) >> 1)*B24;
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int imm24 = branch_offset >> 2;
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ASSERT(is_int24(imm24));
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emit(15 << 28 | B27 | B25 | h | (imm24 & Imm24Mask));
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emit(nv | B27 | B25 | h | (imm24 & Imm24Mask));
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}
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@ -1634,15 +1634,29 @@ void Assembler::stm(BlockAddrMode am,
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// Exception-generating instructions and debugging support.
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void Assembler::stop(const char* msg) {
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// Stops with a non-negative code less than kNumOfWatchedStops support
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// enabling/disabling and a counter feature. See simulator-arm.h .
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void Assembler::stop(const char* msg, Condition cond, int32_t code) {
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#ifndef __arm__
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// The simulator handles these special instructions and stops execution.
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emit(15 << 28 | ((intptr_t) msg));
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// See constants-arm.h SoftwareInterruptCodes. Unluckily the Assembler and
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// Simulator do not share constants declaration.
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ASSERT(code >= kDefaultStopCode);
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static const uint32_t kStopInterruptCode = 1 << 23;
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static const uint32_t kMaxStopCode = kStopInterruptCode - 1;
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// The Simulator will handle the stop instruction and get the message address.
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// It expects to find the address just after the svc instruction.
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BlockConstPoolFor(2);
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if (code >= 0) {
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svc(kStopInterruptCode + code, cond);
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} else {
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svc(kStopInterruptCode + kMaxStopCode, cond);
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}
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emit(reinterpret_cast<Instr>(msg));
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#else // def __arm__
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#ifdef CAN_USE_ARMV5_INSTRUCTIONS
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bkpt(0);
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#else // ndef CAN_USE_ARMV5_INSTRUCTIONS
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swi(0x9f0001);
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svc(0x9f0001);
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#endif // ndef CAN_USE_ARMV5_INSTRUCTIONS
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#endif // def __arm__
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}
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@ -1654,7 +1668,7 @@ void Assembler::bkpt(uint32_t imm16) { // v5 and above
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}
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void Assembler::swi(uint32_t imm24, Condition cond) {
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void Assembler::svc(uint32_t imm24, Condition cond) {
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ASSERT(is_uint24(imm24));
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emit(cond | 15*B24 | imm24);
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}
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@ -904,10 +904,13 @@ class Assembler : public Malloced {
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void stm(BlockAddrMode am, Register base, RegList src, Condition cond = al);
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// Exception-generating instructions and debugging support
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void stop(const char* msg);
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static const int kDefaultStopCode = -1;
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void stop(const char* msg,
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Condition cond = al,
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int32_t code = kDefaultStopCode);
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void bkpt(uint32_t imm16); // v5 and above
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void swi(uint32_t imm24, Condition cond = al);
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void svc(uint32_t imm24, Condition cond = al);
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// Coprocessor instructions
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@ -186,12 +186,18 @@ enum Shift {
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// Special Software Interrupt codes when used in the presence of the ARM
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// simulator.
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// svc (formerly swi) provides a 24bit immediate value. Use bits 22:0 for
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// standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature.
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enum SoftwareInterruptCodes {
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// transition to C code
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call_rt_redirected = 0x10,
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// break point
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break_point = 0x20
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break_point = 0x20,
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// stop
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stop = 1 << 23
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};
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static const int32_t kStopCodeMask = stop - 1;
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static const uint32_t kMaxStopCode = stop - 1;
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// Type of VFP register. Determines register encoding.
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@ -325,7 +331,7 @@ class Instr {
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inline int SImmed24Field() const { return ((InstructionBits() << 8) >> 8); }
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// Fields used in Software interrupt instructions
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inline SoftwareInterruptCodes SwiField() const {
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inline SoftwareInterruptCodes SvcField() const {
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return static_cast<SoftwareInterruptCodes>(Bits(23, 0));
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}
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@ -70,7 +70,7 @@ void CPU::FlushICache(void* start, size_t size) {
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// __arm__ may be defined in thumb mode.
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register uint32_t scno asm("r7") = __ARM_NR_cacheflush;
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asm volatile(
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"swi 0x0"
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"svc 0x0"
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: "=r" (beg)
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: "0" (beg), "r" (end), "r" (flg), "r" (scno));
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#else
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@ -83,7 +83,7 @@ void CPU::FlushICache(void* start, size_t size) {
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".ARM \n"
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"1: push {r7} \n\t"
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"mov r7, %4 \n\t"
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"swi 0x0 \n\t"
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"svc 0x0 \n\t"
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"pop {r7} \n\t"
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"@ Enter THUMB Mode\n\t"
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"adr r3, 2f+1 \n\t"
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@ -98,20 +98,20 @@ void CPU::FlushICache(void* start, size_t size) {
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#if defined (__arm__) && !defined(__thumb__)
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// __arm__ may be defined in thumb mode.
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asm volatile(
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"swi %1"
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"svc %1"
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: "=r" (beg)
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: "i" (__ARM_NR_cacheflush), "0" (beg), "r" (end), "r" (flg));
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#else
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// Do not use the value of __ARM_NR_cacheflush in the inline assembly
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// below, because the thumb mode value would be used, which would be
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// wrong, since we switch to ARM mode before executing the swi instruction
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// wrong, since we switch to ARM mode before executing the svc instruction
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asm volatile(
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"@ Enter ARM Mode \n\t"
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"adr r3, 1f \n\t"
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"bx r3 \n\t"
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".ALIGN 4 \n\t"
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".ARM \n"
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"1: swi 0x9f0002 \n"
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"1: svc 0x9f0002 \n"
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"@ Enter THUMB Mode\n\t"
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"adr r3, 2f+1 \n\t"
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"bx r3 \n\t"
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@ -108,7 +108,7 @@ class Decoder {
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void PrintShiftImm(Instr* instr);
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void PrintShiftSat(Instr* instr);
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void PrintPU(Instr* instr);
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void PrintSoftwareInterrupt(SoftwareInterruptCodes swi);
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void PrintSoftwareInterrupt(SoftwareInterruptCodes svc);
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// Handle formatting of instructions and their options.
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int FormatRegister(Instr* instr, const char* option);
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@ -126,8 +126,8 @@ class Decoder {
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void DecodeType4(Instr* instr);
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void DecodeType5(Instr* instr);
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void DecodeType6(Instr* instr);
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void DecodeType7(Instr* instr);
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void DecodeUnconditional(Instr* instr);
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// Type 7 includes special Debugger instructions.
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int DecodeType7(Instr* instr);
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// For VFP support.
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void DecodeTypeVFP(Instr* instr);
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void DecodeType6CoprocessorIns(Instr* instr);
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@ -290,8 +290,8 @@ void Decoder::PrintPU(Instr* instr) {
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// Print SoftwareInterrupt codes. Factoring this out reduces the complexity of
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// the FormatOption method.
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void Decoder::PrintSoftwareInterrupt(SoftwareInterruptCodes swi) {
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switch (swi) {
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void Decoder::PrintSoftwareInterrupt(SoftwareInterruptCodes svc) {
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switch (svc) {
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case call_rt_redirected:
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Print("call_rt_redirected");
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return;
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@ -299,9 +299,16 @@ void Decoder::PrintSoftwareInterrupt(SoftwareInterruptCodes swi) {
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Print("break_point");
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return;
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default:
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if (svc >= stop) {
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out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
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"%d - 0x%x",
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svc & kStopCodeMask,
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svc & kStopCodeMask);
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} else {
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out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
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"%d",
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swi);
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svc);
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}
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return;
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}
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}
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@ -553,9 +560,9 @@ int Decoder::FormatOption(Instr* instr, const char* format) {
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PrintShiftRm(instr);
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return 8;
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}
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} else if (format[1] == 'w') { // 'swi
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ASSERT(STRING_STARTS_WITH(format, "swi"));
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PrintSoftwareInterrupt(instr->SwiField());
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} else if (format[1] == 'v') { // 'svc
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ASSERT(STRING_STARTS_WITH(format, "svc"));
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PrintSoftwareInterrupt(instr->SvcField());
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return 3;
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} else if (format[1] == 'i') { // 'sign: signed extra loads and stores
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ASSERT(STRING_STARTS_WITH(format, "sign"));
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@ -1004,72 +1011,27 @@ void Decoder::DecodeType6(Instr* instr) {
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}
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void Decoder::DecodeType7(Instr* instr) {
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int Decoder::DecodeType7(Instr* instr) {
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if (instr->Bit(24) == 1) {
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Format(instr, "swi'cond 'swi");
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if (instr->SvcField() >= stop) {
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Format(instr, "stop'cond 'svc");
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// Also print the stop message. Its address is encoded
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// in the following 4 bytes.
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out_buffer_pos_ +=
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v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
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"\n %p %08x stop message: %s",
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reinterpret_cast<int32_t*>(instr + Instr::kInstrSize),
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*reinterpret_cast<char**>(instr + Instr::kInstrSize),
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*reinterpret_cast<char**>(instr + Instr::kInstrSize));
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// We have decoded 2 * Instr::kInstrSize bytes.
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return 2 * Instr::kInstrSize;
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} else {
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Format(instr, "svc'cond 'svc");
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}
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} else {
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DecodeTypeVFP(instr);
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}
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}
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void Decoder::DecodeUnconditional(Instr* instr) {
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if (instr->Bits(7, 4) == 0xB && instr->Bits(27, 25) == 0 && instr->HasL()) {
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Format(instr, "'memop'h'pu 'rd, ");
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bool immediate = instr->HasB();
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switch (instr->PUField()) {
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case 0: {
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// Post index, negative.
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if (instr->HasW()) {
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Unknown(instr);
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break;
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}
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if (immediate) {
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Format(instr, "['rn], #-'imm12");
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} else {
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Format(instr, "['rn], -'rm");
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}
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break;
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}
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case 1: {
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// Post index, positive.
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if (instr->HasW()) {
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Unknown(instr);
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break;
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}
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if (immediate) {
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Format(instr, "['rn], #+'imm12");
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} else {
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Format(instr, "['rn], +'rm");
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}
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break;
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}
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case 2: {
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// Pre index or offset, negative.
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if (immediate) {
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Format(instr, "['rn, #-'imm12]'w");
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} else {
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Format(instr, "['rn, -'rm]'w");
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}
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break;
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}
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case 3: {
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// Pre index or offset, positive.
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if (immediate) {
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Format(instr, "['rn, #+'imm12]'w");
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} else {
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Format(instr, "['rn, +'rm]'w");
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}
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break;
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}
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default: {
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// The PU field is a 2-bit field.
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UNREACHABLE();
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break;
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}
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}
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return;
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}
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Format(instr, "break 'msg");
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return Instr::kInstrSize;
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}
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@ -1332,7 +1294,7 @@ int Decoder::InstructionDecode(byte* instr_ptr) {
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"%08x ",
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instr->InstructionBits());
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if (instr->ConditionField() == special_condition) {
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DecodeUnconditional(instr);
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UNIMPLEMENTED();
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return Instr::kInstrSize;
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}
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switch (instr->TypeField()) {
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@ -1362,8 +1324,7 @@ int Decoder::InstructionDecode(byte* instr_ptr) {
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break;
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}
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case 7: {
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DecodeType7(instr);
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break;
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return DecodeType7(instr);
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}
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default: {
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// The type field is 3-bits in the ARM encoding.
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@ -112,15 +112,29 @@ static void InitializeCoverage() {
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void Debugger::Stop(Instr* instr) {
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char* str = reinterpret_cast<char*>(instr->InstructionBits() & 0x0fffffff);
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if (strlen(str) > 0) {
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// Get the stop code.
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uint32_t code = instr->SvcField() & kStopCodeMask;
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// Retrieve the encoded address, which comes just after this stop.
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char** msg_address =
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reinterpret_cast<char**>(sim_->get_pc() + Instr::kInstrSize);
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char* msg = *msg_address;
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ASSERT(msg != NULL);
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// Update this stop description.
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if (isWatchedStop(code) && !watched_stops[code].desc) {
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watched_stops[code].desc = msg;
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}
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if (strlen(msg) > 0) {
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if (coverage_log != NULL) {
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fprintf(coverage_log, "%s\n", str);
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fprintf(coverage_log, "%s\n", msg);
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fflush(coverage_log);
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}
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instr->SetInstructionBits(0xe1a00000); // Overwrite with nop.
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// Overwrite the instruction and address with nops.
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instr->SetInstructionBits(kNopInstr);
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reinterpret_cast<Instr*>(msg_address)->SetInstructionBits(kNopInstr);
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}
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sim_->set_pc(sim_->get_pc() + Instr::kInstrSize);
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sim_->set_pc(sim_->get_pc() + 2 * Instr::kInstrSize);
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}
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#else // ndef GENERATED_CODE_COVERAGE
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@ -130,9 +144,16 @@ static void InitializeCoverage() {
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void Debugger::Stop(Instr* instr) {
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const char* str = (const char*)(instr->InstructionBits() & 0x0fffffff);
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PrintF("Simulator hit %s\n", str);
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sim_->set_pc(sim_->get_pc() + Instr::kInstrSize);
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// Get the stop code.
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uint32_t code = instr->SvcField() & kStopCodeMask;
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// Retrieve the encoded address, which comes just after this stop.
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char* msg = *reinterpret_cast<char**>(sim_->get_pc() + Instr::kInstrSize);
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// Update this stop description.
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if (sim_->isWatchedStop(code) && !sim_->watched_stops[code].desc) {
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sim_->watched_stops[code].desc = msg;
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}
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PrintF("Simulator hit %s\n", msg);
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sim_->set_pc(sim_->get_pc() + 2 * Instr::kInstrSize);
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Debug();
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}
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#endif
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@ -359,6 +380,7 @@ void Debugger::Debug() {
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// use a reasonably large buffer
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v8::internal::EmbeddedVector<char, 256> buffer;
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byte* prev = NULL;
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byte* cur = NULL;
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byte* end = NULL;
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@ -368,9 +390,9 @@ void Debugger::Debug() {
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} else if (argc == 2) {
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int32_t value;
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if (GetValue(arg1, &value)) {
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cur = reinterpret_cast<byte*>(value);
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// no length parameter passed, assume 10 instructions
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end = cur + (10 * Instr::kInstrSize);
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cur = reinterpret_cast<byte*>(sim_->get_pc());
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// Disassemble <arg1> instructions.
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end = cur + (value * Instr::kInstrSize);
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}
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} else {
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int32_t value1;
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@ -382,10 +404,10 @@ void Debugger::Debug() {
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}
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while (cur < end) {
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dasm.InstructionDecode(buffer, cur);
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prev = cur;
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cur += dasm.InstructionDecode(buffer, cur);
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PrintF(" 0x%08x %s\n",
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reinterpret_cast<intptr_t>(cur), buffer.start());
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cur += Instr::kInstrSize;
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reinterpret_cast<intptr_t>(prev), buffer.start());
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}
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} else if (strcmp(cmd, "gdb") == 0) {
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PrintF("relinquishing control to gdb\n");
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@ -418,13 +440,58 @@ void Debugger::Debug() {
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PrintF("OVERFLOW flag: %d; ", sim_->overflow_vfp_flag_);
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PrintF("UNDERFLOW flag: %d; ", sim_->underflow_vfp_flag_);
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PrintF("INEXACT flag: %d; ", sim_->inexact_vfp_flag_);
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} else if (strcmp(cmd, "unstop") == 0) {
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intptr_t stop_pc = sim_->get_pc() - Instr::kInstrSize;
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} else if (strcmp(cmd, "stop") == 0) {
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int32_t value;
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intptr_t stop_pc = sim_->get_pc() - 2 * Instr::kInstrSize;
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Instr* stop_instr = reinterpret_cast<Instr*>(stop_pc);
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if (stop_instr->ConditionField() == special_condition) {
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Instr* msg_address =
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reinterpret_cast<Instr*>(stop_pc + Instr::kInstrSize);
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if ((argc == 2) && (strcmp(arg1, "unstop") == 0)) {
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// Remove the current stop.
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if (sim_->isStopInstruction(stop_instr)) {
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stop_instr->SetInstructionBits(kNopInstr);
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msg_address->SetInstructionBits(kNopInstr);
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} else {
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PrintF("Not at debugger stop.");
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PrintF("Not at debugger stop.\n");
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}
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} else if (argc == 3) {
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// Print information about all/the specified breakpoint(s).
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if (strcmp(arg1, "info") == 0) {
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if (strcmp(arg2, "all") == 0) {
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PrintF("Stop information:\n");
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for (uint32_t i = 0; i < sim_->kNumOfWatchedStops; i++) {
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sim_->PrintStopInfo(i);
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}
|
||||
} else if (GetValue(arg2, &value)) {
|
||||
sim_->PrintStopInfo(value);
|
||||
} else {
|
||||
PrintF("Unrecognized argument.\n");
|
||||
}
|
||||
} else if (strcmp(arg1, "enable") == 0) {
|
||||
// Enable all/the specified breakpoint(s).
|
||||
if (strcmp(arg2, "all") == 0) {
|
||||
for (uint32_t i = 0; i < sim_->kNumOfWatchedStops; i++) {
|
||||
sim_->EnableStop(i);
|
||||
}
|
||||
} else if (GetValue(arg2, &value)) {
|
||||
sim_->EnableStop(value);
|
||||
} else {
|
||||
PrintF("Unrecognized argument.\n");
|
||||
}
|
||||
} else if (strcmp(arg1, "disable") == 0) {
|
||||
// Disable all/the specified breakpoint(s).
|
||||
if (strcmp(arg2, "all") == 0) {
|
||||
for (uint32_t i = 0; i < sim_->kNumOfWatchedStops; i++) {
|
||||
sim_->DisableStop(i);
|
||||
}
|
||||
} else if (GetValue(arg2, &value)) {
|
||||
sim_->DisableStop(value);
|
||||
} else {
|
||||
PrintF("Unrecognized argument.\n");
|
||||
}
|
||||
}
|
||||
} else {
|
||||
PrintF("Wrong usage. Use help command for more information.\n");
|
||||
}
|
||||
} else if ((strcmp(cmd, "t") == 0) || strcmp(cmd, "trace") == 0) {
|
||||
::v8::internal::FLAG_trace_sim = !::v8::internal::FLAG_trace_sim;
|
||||
@ -455,11 +522,29 @@ void Debugger::Debug() {
|
||||
PrintF(" set a break point on the address\n");
|
||||
PrintF("del\n");
|
||||
PrintF(" delete the breakpoint\n");
|
||||
PrintF("unstop\n");
|
||||
PrintF(" ignore the stop instruction at the current location");
|
||||
PrintF(" from now on\n");
|
||||
PrintF("trace (alias 't')\n");
|
||||
PrintF(" toogle the tracing of all executed statements\n");
|
||||
PrintF("stop feature:\n");
|
||||
PrintF(" Description:\n");
|
||||
PrintF(" Stops are debug instructions inserted by\n");
|
||||
PrintF(" the Assembler::stop() function.\n");
|
||||
PrintF(" When hitting a stop, the Simulator will\n");
|
||||
PrintF(" stop and and give control to the Debugger.\n");
|
||||
PrintF(" The first %d stop codes are watched:\n",
|
||||
Simulator::kNumOfWatchedStops);
|
||||
PrintF(" - They can be enabled / disabled: the Simulator\n");
|
||||
PrintF(" will / won't stop when hitting them.\n");
|
||||
PrintF(" - The Simulator keeps track of how many times they \n");
|
||||
PrintF(" are met. (See the info command.) Going over a\n");
|
||||
PrintF(" disabled stop still increases its counter. \n");
|
||||
PrintF(" Commands:\n");
|
||||
PrintF(" stop info all/<code> : print infos about number <code>\n");
|
||||
PrintF(" or all stop(s).\n");
|
||||
PrintF(" stop enable/disable all/<code> : enables / disables\n");
|
||||
PrintF(" all or number <code> stop(s)\n");
|
||||
PrintF(" stop unstop\n");
|
||||
PrintF(" ignore the stop instruction at the current location\n");
|
||||
PrintF(" from now on\n");
|
||||
} else {
|
||||
PrintF("Unknown command: %s\n", cmd);
|
||||
}
|
||||
@ -643,9 +728,9 @@ Simulator::Simulator() {
|
||||
// the simulator. The external reference will be a function compiled for the
|
||||
// host architecture. We need to call that function instead of trying to
|
||||
// execute it with the simulator. We do that by redirecting the external
|
||||
// reference to a swi (software-interrupt) instruction that is handled by
|
||||
// reference to a svc (Supervisor Call) instruction that is handled by
|
||||
// the simulator. We write the original destination of the jump just at a known
|
||||
// offset from the swi instruction so the simulator knows what to call.
|
||||
// offset from the svc instruction so the simulator knows what to call.
|
||||
class Redirection {
|
||||
public:
|
||||
Redirection(void* external_function, bool fp_return)
|
||||
@ -1434,8 +1519,8 @@ typedef double (*SimulatorRuntimeFPCall)(int32_t arg0,
|
||||
// Software interrupt instructions are used by the simulator to call into the
|
||||
// C-based V8 runtime.
|
||||
void Simulator::SoftwareInterrupt(Instr* instr) {
|
||||
int swi = instr->SwiField();
|
||||
switch (swi) {
|
||||
int svc = instr->SvcField();
|
||||
switch (svc) {
|
||||
case call_rt_redirected: {
|
||||
// Check if stack is aligned. Error if not aligned is reported below to
|
||||
// include information on the function called.
|
||||
@ -1505,11 +1590,100 @@ void Simulator::SoftwareInterrupt(Instr* instr) {
|
||||
dbg.Debug();
|
||||
break;
|
||||
}
|
||||
// stop uses all codes greater than 1 << 23.
|
||||
default: {
|
||||
if (svc >= (1 << 23)) {
|
||||
uint32_t code = svc & kStopCodeMask;
|
||||
if (isWatchedStop(code)) {
|
||||
IncreaseStopCounter(code);
|
||||
}
|
||||
// Stop if it is enabled, otherwise go on jumping over the stop
|
||||
// and the message address.
|
||||
if (isEnabledStop(code)) {
|
||||
Debugger dbg(this);
|
||||
dbg.Stop(instr);
|
||||
} else {
|
||||
set_pc(get_pc() + 2 * Instr::kInstrSize);
|
||||
}
|
||||
} else {
|
||||
// This is not a valid svc code.
|
||||
UNREACHABLE();
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// Stop helper functions.
|
||||
bool Simulator::isStopInstruction(Instr* instr) {
|
||||
return (instr->Bits(27, 24) == 0xF) && (instr->SvcField() >= stop);
|
||||
}
|
||||
|
||||
|
||||
bool Simulator::isWatchedStop(uint32_t code) {
|
||||
ASSERT(code <= kMaxStopCode);
|
||||
return code < kNumOfWatchedStops;
|
||||
}
|
||||
|
||||
|
||||
bool Simulator::isEnabledStop(uint32_t code) {
|
||||
ASSERT(code <= kMaxStopCode);
|
||||
// Unwatched stops are always enabled.
|
||||
return !isWatchedStop(code) ||
|
||||
!(watched_stops[code].count & kStopDisabledBit);
|
||||
}
|
||||
|
||||
|
||||
void Simulator::EnableStop(uint32_t code) {
|
||||
ASSERT(isWatchedStop(code));
|
||||
if (!isEnabledStop(code)) {
|
||||
watched_stops[code].count &= ~kStopDisabledBit;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void Simulator::DisableStop(uint32_t code) {
|
||||
ASSERT(isWatchedStop(code));
|
||||
if (isEnabledStop(code)) {
|
||||
watched_stops[code].count |= kStopDisabledBit;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void Simulator::IncreaseStopCounter(uint32_t code) {
|
||||
ASSERT(code <= kMaxStopCode);
|
||||
ASSERT(isWatchedStop(code));
|
||||
if ((watched_stops[code].count & ~(1 << 31)) == 0x7fffffff) {
|
||||
PrintF("Stop counter for code %i has overflowed.\n"
|
||||
"Enabling this code and reseting the counter to 0.\n", code);
|
||||
watched_stops[code].count = 0;
|
||||
EnableStop(code);
|
||||
} else {
|
||||
watched_stops[code].count++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// Print a stop status.
|
||||
void Simulator::PrintStopInfo(uint32_t code) {
|
||||
ASSERT(code <= kMaxStopCode);
|
||||
if (!isWatchedStop(code)) {
|
||||
PrintF("Stop not watched.");
|
||||
} else {
|
||||
const char* state = isEnabledStop(code) ? "Enabled" : "Disabled";
|
||||
int32_t count = watched_stops[code].count & ~kStopDisabledBit;
|
||||
// Don't print the state of unused breakpoints.
|
||||
if (count != 0) {
|
||||
if (watched_stops[code].desc) {
|
||||
PrintF("stop %i - 0x%x: \t%s, \tcounter = %i, \t%s\n",
|
||||
code, code, state, count, watched_stops[code].desc);
|
||||
} else {
|
||||
PrintF("stop %i - 0x%x: \t%s, \tcounter = %i\n",
|
||||
code, code, state, count);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -2216,73 +2390,6 @@ void Simulator::DecodeType7(Instr* instr) {
|
||||
}
|
||||
|
||||
|
||||
void Simulator::DecodeUnconditional(Instr* instr) {
|
||||
if (instr->Bits(7, 4) == 0x0B && instr->Bits(27, 25) == 0 && instr->HasL()) {
|
||||
// Load halfword instruction, either register or immediate offset.
|
||||
int rd = instr->RdField();
|
||||
int rn = instr->RnField();
|
||||
int32_t rn_val = get_register(rn);
|
||||
int32_t addr = 0;
|
||||
int32_t offset;
|
||||
if (instr->Bit(22) == 0) {
|
||||
// Register offset.
|
||||
int rm = instr->RmField();
|
||||
offset = get_register(rm);
|
||||
} else {
|
||||
// Immediate offset
|
||||
offset = instr->Bits(3, 0) + (instr->Bits(11, 8) << 4);
|
||||
}
|
||||
switch (instr->PUField()) {
|
||||
case 0: {
|
||||
// Post index, negative.
|
||||
ASSERT(!instr->HasW());
|
||||
addr = rn_val;
|
||||
rn_val -= offset;
|
||||
set_register(rn, rn_val);
|
||||
break;
|
||||
}
|
||||
case 1: {
|
||||
// Post index, positive.
|
||||
ASSERT(!instr->HasW());
|
||||
addr = rn_val;
|
||||
rn_val += offset;
|
||||
set_register(rn, rn_val);
|
||||
break;
|
||||
}
|
||||
case 2: {
|
||||
// Pre index or offset, negative.
|
||||
rn_val -= offset;
|
||||
addr = rn_val;
|
||||
if (instr->HasW()) {
|
||||
set_register(rn, rn_val);
|
||||
}
|
||||
break;
|
||||
}
|
||||
case 3: {
|
||||
// Pre index or offset, positive.
|
||||
rn_val += offset;
|
||||
addr = rn_val;
|
||||
if (instr->HasW()) {
|
||||
set_register(rn, rn_val);
|
||||
}
|
||||
break;
|
||||
}
|
||||
default: {
|
||||
// The PU field is a 2-bit field.
|
||||
UNREACHABLE();
|
||||
break;
|
||||
}
|
||||
}
|
||||
// Not sign extending, so load as unsigned.
|
||||
uint16_t halfword = ReadH(addr, instr);
|
||||
set_register(rd, halfword);
|
||||
} else {
|
||||
Debugger dbg(this);
|
||||
dbg.Stop(instr);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// void Simulator::DecodeTypeVFP(Instr* instr)
|
||||
// The Following ARMv7 VFPv instructions are currently supported.
|
||||
// vmov :Sn = Rt
|
||||
@ -2655,7 +2762,7 @@ void Simulator::InstructionDecode(Instr* instr) {
|
||||
PrintF(" 0x%08x %s\n", reinterpret_cast<intptr_t>(instr), buffer.start());
|
||||
}
|
||||
if (instr->ConditionField() == special_condition) {
|
||||
DecodeUnconditional(instr);
|
||||
UNIMPLEMENTED();
|
||||
} else if (ConditionallyExecute(instr)) {
|
||||
switch (instr->TypeField()) {
|
||||
case 0:
|
||||
|
||||
@ -226,6 +226,15 @@ class Simulator {
|
||||
void HandleRList(Instr* instr, bool load);
|
||||
void SoftwareInterrupt(Instr* instr);
|
||||
|
||||
// Stop helper functions.
|
||||
inline bool isStopInstruction(Instr* instr);
|
||||
inline bool isWatchedStop(uint32_t bkpt_code);
|
||||
inline bool isEnabledStop(uint32_t bkpt_code);
|
||||
inline void EnableStop(uint32_t bkpt_code);
|
||||
inline void DisableStop(uint32_t bkpt_code);
|
||||
inline void IncreaseStopCounter(uint32_t bkpt_code);
|
||||
void PrintStopInfo(uint32_t code);
|
||||
|
||||
// Read and write memory.
|
||||
inline uint8_t ReadBU(int32_t addr);
|
||||
inline int8_t ReadB(int32_t addr);
|
||||
@ -252,7 +261,6 @@ class Simulator {
|
||||
void DecodeType5(Instr* instr);
|
||||
void DecodeType6(Instr* instr);
|
||||
void DecodeType7(Instr* instr);
|
||||
void DecodeUnconditional(Instr* instr);
|
||||
|
||||
// Support for VFP.
|
||||
void DecodeTypeVFP(Instr* instr);
|
||||
@ -317,6 +325,23 @@ class Simulator {
|
||||
// Registered breakpoints.
|
||||
Instr* break_pc_;
|
||||
instr_t break_instr_;
|
||||
|
||||
// A stop is watched if its code is less than kNumOfWatchedStops.
|
||||
// Only watched stops support enabling/disabling and the counter feature.
|
||||
static const uint32_t kNumOfWatchedStops = 256;
|
||||
|
||||
// Breakpoint is disabled if bit 31 is set.
|
||||
static const uint32_t kStopDisabledBit = 1 << 31;
|
||||
|
||||
// A stop is enabled, meaning the simulator will stop when meeting the
|
||||
// instruction, if bit 31 of watched_stops[code].count is unset.
|
||||
// The value watched_stops[code].count & ~(1 << 31) indicates how many times
|
||||
// the breakpoint was hit or gone through.
|
||||
struct StopCoundAndDesc {
|
||||
uint32_t count;
|
||||
char* desc;
|
||||
};
|
||||
StopCoundAndDesc watched_stops[kNumOfWatchedStops];
|
||||
};
|
||||
|
||||
} } // namespace assembler::arm
|
||||
|
||||
Loading…
Reference in New Issue
Block a user