AuroraMiddleware/v8
1
0
Fork 0
Code Issues 2 Pull Requests Releases Wiki Activity

Revert "[wasm] reduce registers for simd packing in ia32"

Browse Source 
This reverts commit 82d447228b.

Reason for revert: we want to keep register allocation general simd binary case

Original change's description:
> [wasm] reduce registers for simd packing in ia32
>
> R=​gdeepti@chromium.org
> BUG=v8:6020
>
> Change-Id: I01644bca95ff5715122c1bc3923024145586a6fd
> Reviewed-on: https://chromium-review.googlesource.com/1112070
> Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
> Commit-Queue: Aseem Garg <aseemgarg@chromium.org>
> Cr-Commit-Position: refs/heads/master@{#53985}

TBR=bbudge@chromium.org,gdeepti@chromium.org,aseemgarg@chromium.org,jing.bao@intel.com

Bug: v8:6020
Change-Id: I878ca82b893fc019e9f769ab2b218fdbaad5f701
Reviewed-on: https://chromium-review.googlesource.com/1114157
Commit-Queue: Aseem Garg <aseemgarg@chromium.org>
Reviewed-by: Aseem Garg <aseemgarg@chromium.org>
Reviewed-by: Bill Budge <bbudge@chromium.org>
Cr-Commit-Position: refs/heads/master@{#54011}
This commit is contained in:
Aseem Garg 2018-06-25 14:04:22 -07:00 committed by Commit Bot
parent b8626ca445
commit 21e5229c5f
2 changed files with 22 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/compiler/ia32/code-generator-ia32.cc
View File

@ -3001,6 +3001,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
case kAVXI8x16UConvertI16x8: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
CpuFeatureScope avx_scope(tasm(), AVX);
XMMRegister dst = i.OutputSimd128Register();
// Change negative lanes to 0x7FFF

24
src/compiler/ia32/instruction-selector-ia32.cc
View File

@ -193,7 +193,7 @@ void VisitRROFloat(InstructionSelector* selector, Node* node,
InstructionOperand operand0 = g.UseRegister(node->InputAt(0));
InstructionOperand operand1 = g.Use(node->InputAt(1));
if (selector->IsSupported(AVX)) {
selector->Emit(avx_opcode, g.DefineSameAsFirst(node), operand0, operand1);
selector->Emit(avx_opcode, g.DefineAsRegister(node), operand0, operand1);
} else {
selector->Emit(sse_opcode, g.DefineSameAsFirst(node), operand0, operand1);
}
@ -1765,7 +1765,6 @@ VISIT_ATOMIC_BINOP(Xor)
V(I16x8Ne) \
V(I16x8GtS) \
V(I16x8GeS) \
V(I16x8UConvertI32x4) \
V(I16x8AddSaturateU) \
V(I16x8SubSaturateU) \
V(I16x8MinU) \
@ -1783,7 +1782,6 @@ VISIT_ATOMIC_BINOP(Xor)
V(I8x16Ne) \
V(I8x16GtS) \
V(I8x16GeS) \
V(I8x16UConvertI16x8) \
V(I8x16AddSaturateU) \
V(I8x16SubSaturateU) \
V(I8x16MinU) \
@ -2014,6 +2012,26 @@ SIMD_BINOP_LIST(VISIT_SIMD_BINOP)
#undef VISIT_SIMD_BINOP
#undef SIMD_BINOP_LIST
void VisitPack(InstructionSelector* selector, Node* node, ArchOpcode avx_opcode,
ArchOpcode sse_opcode) {
IA32OperandGenerator g(selector);
InstructionOperand operand0 = g.UseRegister(node->InputAt(0));
InstructionOperand operand1 = g.Use(node->InputAt(1));
if (selector->IsSupported(AVX)) {
selector->Emit(avx_opcode, g.DefineSameAsFirst(node), operand0, operand1);
} else {
selector->Emit(sse_opcode, g.DefineSameAsFirst(node), operand0, operand1);
}
}
void InstructionSelector::VisitI16x8UConvertI32x4(Node* node) {
VisitPack(this, node, kAVXI16x8UConvertI32x4, kSSEI16x8UConvertI32x4);
}
void InstructionSelector::VisitI8x16UConvertI16x8(Node* node) {
VisitPack(this, node, kAVXI8x16UConvertI16x8, kSSEI8x16UConvertI16x8);
}
void InstructionSelector::VisitInt32AbsWithOverflow(Node* node) {
UNREACHABLE();
}