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Partial revert of r21901 (2nd attempt)

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Only disable runtime check for sse2 if __SSE2__ is not defined. This
is required for the x87 port

BUG=none
LOG=n
R=jkummerow@chromium.org

Review URL: https://codereview.chromium.org/331803006

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21938 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
This commit is contained in:
jochen@chromium.org 2014-06-23 13:30:03 +00:00
parent f61854fe0a
commit 23521436fb
2 changed files with 37 additions and 1 deletions
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8
src/base/atomicops_internals_x86_gcc.cc
View File

@ -42,6 +42,9 @@ namespace base {
// default values should hopefully be pretty safe.
struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = {
false, // bug can't exist before process spawns multiple threads
#if !defined(__SSE2__)
false, // no SSE2
#endif
};
} } // namespace v8::base
@ -87,6 +90,11 @@ void AtomicOps_Internalx86CPUFeaturesInit() {
} else {
AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false;
}
#if !defined(__SSE2__)
// edx bit 26 is SSE2 which we use to tell use whether we can use mfence
AtomicOps_Internalx86CPUFeatures.has_sse2 = ((edx >> 26) & 1);
#endif
}
class AtomicOpsx86Initializer {

30
src/base/atomicops_internals_x86_gcc.h
View File

@ -17,6 +17,9 @@ namespace base {
struct AtomicOps_x86CPUFeatureStruct {
bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do lfence
// after acquire compare-and-swap.
#if !defined(__SSE2__)
bool has_sse2; // Processor has SSE2.
#endif
};
extern struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures;
@ -91,7 +94,10 @@ inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
*ptr = value;
}
// We require SSE2, so mfence is guaranteed to exist.
#if defined(__x86_64__) || defined(__SSE2__)
// 64-bit implementations of memory barrier can be simpler, because it
// "mfence" is guaranteed to exist.
inline void MemoryBarrier() {
__asm__ __volatile__("mfence" : : : "memory");
}
@ -101,6 +107,28 @@ inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
MemoryBarrier();
}
#else
inline void MemoryBarrier() {
if (AtomicOps_Internalx86CPUFeatures.has_sse2) {
__asm__ __volatile__("mfence" : : : "memory");
} else { // mfence is faster but not present on PIII
Atomic32 x = 0;
NoBarrier_AtomicExchange(&x, 0); // acts as a barrier on PIII
}
}
inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
if (AtomicOps_Internalx86CPUFeatures.has_sse2) {
*ptr = value;
__asm__ __volatile__("mfence" : : : "memory");
} else {
NoBarrier_AtomicExchange(ptr, value);
// acts as a barrier on PIII
}
}
#endif
inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
ATOMICOPS_COMPILER_BARRIER();
*ptr = value; // An x86 store acts as a release barrier.