MIPS64: [turbofan] Initial support for Switch.
Port feb2890711
Original commit message:
Adds Switch and Case operators to TurboFan and handles them
appropriately in instruction selection and code generation.
BUG=
Review URL: https://codereview.chromium.org/932683002
Cr-Commit-Position: refs/heads/master@{#26699}
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@ -428,6 +428,9 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
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case kArchJmp:
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AssembleArchJump(i.InputRpo(0));
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break;
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case kArchSwitch:
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AssembleArchSwitch(instr);
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break;
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case kArchNop:
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// don't emit code for nops.
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break;
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@ -916,6 +919,32 @@ void CodeGenerator::AssembleArchJump(BasicBlock::RpoNumber target) {
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}
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void CodeGenerator::AssembleArchSwitch(Instruction* instr) {
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MipsOperandConverter i(this, instr);
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int const kNumLabels = static_cast<int>(instr->InputCount() - 1);
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v8::internal::Assembler::BlockTrampolinePoolScope block_trampoline_pool(
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masm());
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Label here;
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// Ensure that dd-ed labels goes to 8 byte aligned addresses.
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if ((masm()->pc_offset() & 7) == 0) {
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__ nop();
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}
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__ bal(&here);
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__ nop(); // Branch delay slot nop.
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__ bind(&here);
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__ dsll(at, i.InputRegister(0), 3);
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__ daddu(at, at, ra);
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__ ld(at, MemOperand(at, 5 * v8::internal::Assembler::kInstrSize));
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__ jr(at);
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__ nop(); // Branch delay slot nop.
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for (int index = 0; index < kNumLabels; ++index) {
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__ dd(GetLabel(i.InputRpo(index + 1)));
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}
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}
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// Assembles boolean materializations after an instruction.
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void CodeGenerator::AssembleArchBoolean(Instruction* instr,
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FlagsCondition condition) {
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@ -1283,6 +1312,12 @@ void CodeGenerator::AssembleSwap(InstructionOperand* source,
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}
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void CodeGenerator::AssembleJumpTable(Label** targets, size_t target_count) {
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// On 64-bit MIPS we emit the jump tables inline.
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UNREACHABLE();
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}
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void CodeGenerator::AddNopForSmiCodeInlining() {
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// Unused on 32-bit ARM. Still exists on 64-bit arm.
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// TODO(plind): Unclear when this is called now. Understand, fix if needed.
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