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MIPS64: Fix 32bit right shift operators

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Add sign extension for Mips64Shr and Mips64Sar operators.

BUG=

Review-Url: https://codereview.chromium.org/2154703002
Cr-Commit-Position: refs/heads/master@{#37943}
This commit is contained in:
marija.antic 2016-07-21 04:36:28 -07:00 committed by Commit bot
parent 07a0f9ebff
commit 24d432cb82
1 changed files with 4 additions and 0 deletions
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4
src/compiler/mips64/code-generator-mips64.cc
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@ -1131,18 +1131,22 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
case kMips64Shr: case kMips64Shr:
if (instr->InputAt(1)->IsRegister()) { if (instr->InputAt(1)->IsRegister()) {
__ sll(i.InputRegister(0), i.InputRegister(0), 0x0);
__ srlv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); __ srlv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
} else { } else {
int64_t imm = i.InputOperand(1).immediate(); int64_t imm = i.InputOperand(1).immediate();
__ sll(i.InputRegister(0), i.InputRegister(0), 0x0);
__ srl(i.OutputRegister(), i.InputRegister(0), __ srl(i.OutputRegister(), i.InputRegister(0),
static_cast<uint16_t>(imm)); static_cast<uint16_t>(imm));
} }
break; break;
case kMips64Sar: case kMips64Sar:
if (instr->InputAt(1)->IsRegister()) { if (instr->InputAt(1)->IsRegister()) {
__ sll(i.InputRegister(0), i.InputRegister(0), 0x0);
__ srav(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); __ srav(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
} else { } else {
int64_t imm = i.InputOperand(1).immediate(); int64_t imm = i.InputOperand(1).immediate();
__ sll(i.InputRegister(0), i.InputRegister(0), 0x0);
__ sra(i.OutputRegister(), i.InputRegister(0), __ sra(i.OutputRegister(), i.InputRegister(0),
static_cast<uint16_t>(imm)); static_cast<uint16_t>(imm));
} }