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MIPS: disabling rsqrt and recip for mips32r1

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Disabling rsqrt and recip for mips32r1 in assembler, disassembler and simulator

Review URL: https://codereview.chromium.org/1221663006

Cr-Commit-Position: refs/heads/master@{#29425}
This commit is contained in:
Djordje.Pesic 2015-07-01 09:15:34 -07:00 committed by Commit bot
parent e32f9cfc10
commit 2604c75eed
4 changed files with 48 additions and 30 deletions
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4
src/mips/assembler-mips.cc
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@ -2350,21 +2350,25 @@ void Assembler::sqrt_d(FPURegister fd, FPURegister fs) {
void Assembler::rsqrt_s(FPURegister fd, FPURegister fs) {
DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
GenInstrRegister(COP1, S, f0, fs, fd, RSQRT_S);
}
void Assembler::rsqrt_d(FPURegister fd, FPURegister fs) {
DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
GenInstrRegister(COP1, D, f0, fs, fd, RSQRT_D);
}
void Assembler::recip_d(FPURegister fd, FPURegister fs) {
DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
GenInstrRegister(COP1, D, f0, fs, fd, RECIP_D);
}
void Assembler::recip_s(FPURegister fd, FPURegister fs) {
DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
GenInstrRegister(COP1, S, f0, fs, fd, RECIP_S);
}

4
src/mips/simulator-mips.cc
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@ -2711,11 +2711,13 @@ void Simulator::DecodeTypeRegisterDRsType(Instruction* instr,
set_fpu_register_double(fd_reg, fast_sqrt(fs));
break;
case RSQRT_D: {
DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
double result = 1.0 / fast_sqrt(fs);
set_fpu_register_double(fd_reg, result);
break;
}
case RECIP_D: {
DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
double result = 1.0 / fs;
set_fpu_register_double(fd_reg, result);
break;
@ -3117,11 +3119,13 @@ void Simulator::DecodeTypeRegisterSRsType(Instruction* instr,
set_fpu_register_float(fd_reg, fast_sqrt(fs));
break;
case RSQRT_S: {
DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
float result = 1.0 / fast_sqrt(fs);
set_fpu_register_float(fd_reg, result);
break;
}
case RECIP_S: {
DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
float result = 1.0 / fs;
set_fpu_register_float(fd_reg, result);
break;

60
test/cctest/test-assembler-mips.cc
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@ -2511,16 +2511,22 @@ TEST(sqrt_rsqrt_recip) {
__ ldc1(f8, MemOperand(a0, offsetof(TestFloat, c)) );
__ sqrt_s(f6, f2);
__ sqrt_d(f12, f8);
__ rsqrt_d(f14, f8);
__ rsqrt_s(f16, f2);
__ recip_d(f18, f8);
__ recip_s(f20, f2);
if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) {
__ rsqrt_d(f14, f8);
__ rsqrt_s(f16, f2);
__ recip_d(f18, f8);
__ recip_s(f20, f2);
}
__ swc1(f6, MemOperand(a0, offsetof(TestFloat, resultS)) );
__ sdc1(f12, MemOperand(a0, offsetof(TestFloat, resultD)) );
__ swc1(f16, MemOperand(a0, offsetof(TestFloat, resultS1)) );
__ sdc1(f14, MemOperand(a0, offsetof(TestFloat, resultD1)) );
__ swc1(f20, MemOperand(a0, offsetof(TestFloat, resultS2)) );
__ sdc1(f18, MemOperand(a0, offsetof(TestFloat, resultD2)) );
if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) {
__ swc1(f16, MemOperand(a0, offsetof(TestFloat, resultS1)) );
__ sdc1(f14, MemOperand(a0, offsetof(TestFloat, resultD1)) );
__ swc1(f20, MemOperand(a0, offsetof(TestFloat, resultS2)) );
__ sdc1(f18, MemOperand(a0, offsetof(TestFloat, resultD2)) );
}
__ jr(ra);
__ nop();
@ -2541,24 +2547,26 @@ TEST(sqrt_rsqrt_recip) {
CHECK_EQ(test.resultS, outputs_S[i]);
CHECK_EQ(test.resultD, outputs_D[i]);
if (i != 0) {
f1 = test.resultS1 - 1.0F/outputs_S[i];
f1 = (f1 < 0) ? f1 : -f1;
CHECK(f1 <= deltaFloat);
d1 = test.resultD1 - 1.0L/outputs_D[i];
d1 = (d1 < 0) ? d1 : -d1;
CHECK(d1 <= deltaDouble);
f1 = test.resultS2 - 1.0F/inputs_S[i];
f1 = (f1 < 0) ? f1 : -f1;
CHECK(f1 <= deltaFloat);
d1 = test.resultD2 - 1.0L/inputs_D[i];
d1 = (d1 < 0) ? d1 : -d1;
CHECK(d1 <= deltaDouble);
} else {
CHECK_EQ(test.resultS1, 1.0F/outputs_S[i]);
CHECK_EQ(test.resultD1, 1.0L/outputs_D[i]);
CHECK_EQ(test.resultS2, 1.0F/inputs_S[i]);
CHECK_EQ(test.resultD2, 1.0L/inputs_D[i]);
if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) {
if (i != 0) {
f1 = test.resultS1 - 1.0F/outputs_S[i];
f1 = (f1 < 0) ? f1 : -f1;
CHECK(f1 <= deltaFloat);
d1 = test.resultD1 - 1.0L/outputs_D[i];
d1 = (d1 < 0) ? d1 : -d1;
CHECK(d1 <= deltaDouble);
f1 = test.resultS2 - 1.0F/inputs_S[i];
f1 = (f1 < 0) ? f1 : -f1;
CHECK(f1 <= deltaFloat);
d1 = test.resultD2 - 1.0L/inputs_D[i];
d1 = (d1 < 0) ? d1 : -d1;
CHECK(d1 <= deltaDouble);
} else {
CHECK_EQ(test.resultS1, 1.0F/outputs_S[i]);
CHECK_EQ(test.resultD1, 1.0L/outputs_D[i]);
CHECK_EQ(test.resultS2, 1.0F/inputs_S[i]);
CHECK_EQ(test.resultD2, 1.0L/inputs_D[i]);
}
}
}
}

10
test/cctest/test-disasm-mips.cc
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@ -666,11 +666,13 @@ TEST(Type1) {
COMPARE(mul_s(f8, f6, f4), "46043202 mul.s f8, f6, f4");
COMPARE(mul_d(f8, f6, f4), "46243202 mul.d f8, f6, f4");
COMPARE(rsqrt_s(f8, f6), "46003216 rsqrt.s f8, f6");
COMPARE(rsqrt_d(f8, f6), "46203216 rsqrt.d f8, f6");
if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) {
COMPARE(rsqrt_s(f8, f6), "46003216 rsqrt.s f8, f6");
COMPARE(rsqrt_d(f8, f6), "46203216 rsqrt.d f8, f6");
COMPARE(recip_s(f8, f6), "46003215 recip.s f8, f6");
COMPARE(recip_d(f8, f6), "46203215 recip.d f8, f6");
COMPARE(recip_s(f8, f6), "46003215 recip.s f8, f6");
COMPARE(recip_d(f8, f6), "46203215 recip.d f8, f6");
}
COMPARE(mov_s(f6, f4), "46002186 mov.s f6, f4");
COMPARE(mov_d(f6, f4), "46202186 mov.d f6, f4");