[compiler] Add TSAN support for generated code movl and movq

This finishes the TSAN support for loads as we do not use movb or movw
to load from memory

Bug: v8:7790, v8:11600
Change-Id: I3c319da95c24cfa03f4de2367e007fd4cf7dd355
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2953321
Reviewed-by: Jakob Gruber <jgruber@chromium.org>
Commit-Queue: Santiago Aboy Solanes <solanes@chromium.org>
Cr-Commit-Position: refs/heads/master@{#75204}

src/compiler/backend/x64/code-generator-x64.cc

@@ -2262,7 +2262,10 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       EmitOOLTrapIfNeeded(zone(), this, opcode, instr, __ pc_offset());
       if (instr->HasOutput()) {
         if (HasAddressingMode(instr)) {
-          __ movl(i.OutputRegister(), i.MemoryOperand());
+          Operand address(i.MemoryOperand());
+          __ movl(i.OutputRegister(), address);
+          EmitTSANLoadOOLIfNeeded(zone(), this, tasm(), address, i,
+                                  DetermineStubCallMode(), kInt32Size);
         } else {
           if (HasRegisterInput(instr, 0)) {
             __ movl(i.OutputRegister(), i.InputRegister(0));
@@ -2340,7 +2343,10 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
     case kX64Movq:
       EmitOOLTrapIfNeeded(zone(), this, opcode, instr, __ pc_offset());
       if (instr->HasOutput()) {
-        __ movq(i.OutputRegister(), i.MemoryOperand());
+        Operand address(i.MemoryOperand());
+        __ movq(i.OutputRegister(), address);
+        EmitTSANLoadOOLIfNeeded(zone(), this, tasm(), address, i,
+                                DetermineStubCallMode(), kInt64Size);
       } else {
         size_t index = 0;
         Operand operand = i.MemoryOperand(&index);

src/compiler/backend/x64/instruction-selector-x64.cc

@@ -798,13 +798,25 @@ bool TryMergeTruncateInt64ToInt32IntoLoad(InstructionSelector* selector,
         return false;
     }
     X64OperandGenerator g(selector);
+#ifdef V8_IS_TSAN
+    // On TSAN builds we require one scratch register. Because of this we also
+    // have to modify the inputs to take into account possible aliasing and use
+    // UseUniqueRegister which is not required for non-TSAN builds.
+    InstructionOperand temps[] = {g.TempRegister()};
+    size_t temp_count = arraysize(temps);
+    auto reg_kind = OperandGenerator::RegisterUseKind::kUseUniqueRegister;
+#else
+    InstructionOperand* temps = nullptr;
+    size_t temp_count = 0;
+    auto reg_kind = OperandGenerator::RegisterUseKind::kUseRegister;
+#endif  // V8_IS_TSAN
     InstructionOperand outputs[] = {g.DefineAsRegister(node)};
     size_t input_count = 0;
     InstructionOperand inputs[3];
     AddressingMode mode = g.GetEffectiveAddressMemoryOperand(
-        node->InputAt(0), inputs, &input_count);
+        node->InputAt(0), inputs, &input_count, reg_kind);
     opcode |= AddressingModeField::encode(mode);
-    selector->Emit(opcode, 1, outputs, input_count, inputs);
+    selector->Emit(opcode, 1, outputs, input_count, inputs, temp_count, temps);
     return true;
   }
   return false;
@@ -1006,10 +1018,22 @@ bool TryMatchLoadWord64AndShiftRight(InstructionSelector* selector, Node* node,
                                                 AddressOption::kAllowAll);
     if (mleft.matches() && (mleft.displacement() == nullptr ||
                             g.CanBeImmediate(mleft.displacement()))) {
+#ifdef V8_IS_TSAN
+      // On TSAN builds we require one scratch register. Because of this we also
+      // have to modify the inputs to take into account possible aliasing and
+      // use UseUniqueRegister which is not required for non-TSAN builds.
+      InstructionOperand temps[] = {g.TempRegister()};
+      size_t temp_count = arraysize(temps);
+      auto reg_kind = OperandGenerator::RegisterUseKind::kUseUniqueRegister;
+#else
+      InstructionOperand* temps = nullptr;
+      size_t temp_count = 0;
+      auto reg_kind = OperandGenerator::RegisterUseKind::kUseRegister;
+#endif  // V8_IS_TSAN
       size_t input_count = 0;
       InstructionOperand inputs[3];
       AddressingMode mode = g.GetEffectiveAddressMemoryOperand(
-          m.left().node(), inputs, &input_count);
+          m.left().node(), inputs, &input_count, reg_kind);
       if (mleft.displacement() == nullptr) {
         // Make sure that the addressing mode indicates the presence of an
         // immediate displacement. It seems that we never use M1 and M2, but we
@@ -1028,7 +1052,7 @@ bool TryMatchLoadWord64AndShiftRight(InstructionSelector* selector, Node* node,
       }
       InstructionOperand outputs[] = {g.DefineAsRegister(node)};
       InstructionCode code = opcode | AddressingModeField::encode(mode);
-      selector->Emit(code, 1, outputs, input_count, inputs);
+      selector->Emit(code, 1, outputs, input_count, inputs, temp_count, temps);
       return true;
     }
   }

test/benchmarks/benchmarks.status

@@ -33,7 +33,7 @@
   'octane/pdfjs': [PASS, ['mode == debug', SKIP]],
 
   # Slow tests.
-  'kraken/imaging-gaussian-blur': [PASS, SLOW],
+  'kraken/imaging-gaussian-blur': [PASS, SLOW, ['tsan', SKIP]],
   'octane/box2d': [PASS, SLOW],
   'octane/regexp': [PASS, SLOW],
   'octane/typescript': [PASS, SLOW],
@@ -104,7 +104,18 @@
   'octane/typescript': [SKIP],
 }],  # 'predictable'
 
-################################################################################
+['tsan', {
+  # Slow tests.
+  'kraken/audio-beat-detection': [SLOW],
+  'kraken/audio-dft': [SLOW],
+  'kraken/audio-fft': [SLOW],
+  'kraken/audio-oscillator': [SLOW],
+  'octane/pdfjs': [SLOW],
+
+  # Too slow.
+  'octane/mandreel': [SKIP],
+}],  # 'tsan'
+
 ['variant == stress_snapshot', {
   '*': [SKIP],  # only relevant for mjsunit tests.
 }],

test/wasm-spec-tests/wasm-spec-tests.status

@@ -183,4 +183,10 @@
   'proposals/simd/*': [SKIP],
 }],  # no_simd_hardware == True
 
+##############################################################################
+['tsan', {
+  # Too slow.
+  'proposals/simd/simd_f64x2_pmin_pmax': [SKIP],
+}],  # tsan
+
 ]

test/webkit/webkit.status

@@ -82,6 +82,10 @@
   # Too slow.
   'dfg-int-overflow-in-loop': [SKIP],
 }],  # 'arch == s390 or arch == s390x'
+['tsan', {
+  # Too slow.
+  'dfg-int-overflow-in-loop': [SLOW],
+}],  # 'tsan'
 
 ##############################################################################
 ['asan == True', {