From 2669f27daa3bd3f9198b2c0914492755b4eca27f Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Thu, 17 Oct 2019 15:42:01 -0700 Subject: [PATCH] [wasm-simd] Implement i64x2 neg for ia32 Bug: v8:9728 Change-Id: I0b90bf97fc8f57f8b372c3254d585c707da9fe7a Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1865255 Reviewed-by: Deepti Gandluri Commit-Queue: Zhi An Ng Cr-Commit-Position: refs/heads/master@{#64434} --- src/codegen/ia32/macro-assembler-ia32.h | 1 + src/codegen/ia32/sse-instr.h | 1 + src/compiler/backend/ia32/code-generator-ia32.cc | 7 +++++++ src/compiler/backend/ia32/instruction-codes-ia32.h | 1 + src/compiler/backend/ia32/instruction-scheduler-ia32.cc | 1 + src/compiler/backend/ia32/instruction-selector-ia32.cc | 6 ++++++ src/compiler/backend/instruction-selector.cc | 2 +- test/cctest/wasm/test-run-wasm-simd.cc | 2 +- 8 files changed, 19 insertions(+), 2 deletions(-) diff --git a/src/codegen/ia32/macro-assembler-ia32.h b/src/codegen/ia32/macro-assembler-ia32.h index cd3ff6fa8d..cf24194d09 100644 --- a/src/codegen/ia32/macro-assembler-ia32.h +++ b/src/codegen/ia32/macro-assembler-ia32.h @@ -291,6 +291,7 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase { AVX_OP3_XO(Psubb, psubb) AVX_OP3_XO(Psubw, psubw) AVX_OP3_XO(Psubd, psubd) + AVX_OP3_XO(Psubq, psubq) AVX_OP3_XO(Punpcklbw, punpcklbw) AVX_OP3_XO(Punpckhbw, punpckhbw) AVX_OP3_XO(Pxor, pxor) diff --git a/src/codegen/ia32/sse-instr.h b/src/codegen/ia32/sse-instr.h index 87c333d188..836480aad0 100644 --- a/src/codegen/ia32/sse-instr.h +++ b/src/codegen/ia32/sse-instr.h @@ -38,6 +38,7 @@ V(psubb, 66, 0F, F8) \ V(psubw, 66, 0F, F9) \ V(psubd, 66, 0F, FA) \ + V(psubq, 66, 0F, FB) \ V(psubsb, 66, 0F, E8) \ V(psubsw, 66, 0F, E9) \ V(psubusb, 66, 0F, D8) \ diff --git a/src/compiler/backend/ia32/code-generator-ia32.cc b/src/compiler/backend/ia32/code-generator-ia32.cc index b08759d535..ee97f5f729 100644 --- a/src/compiler/backend/ia32/code-generator-ia32.cc +++ b/src/compiler/backend/ia32/code-generator-ia32.cc @@ -2007,6 +2007,13 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( __ Pinsrd(i.OutputSimd128Register(), i.InputOperand(3), lane * 2 + 1); break; } + case kIA32I64x2Neg: { + XMMRegister dst = i.OutputSimd128Register(); + Operand src = i.InputOperand(0); + __ Pxor(dst, dst); + __ Psubq(dst, src); + break; + } case kSSEF32x4Splat: { DCHECK_EQ(i.OutputDoubleRegister(), i.InputDoubleRegister(0)); XMMRegister dst = i.OutputSimd128Register(); diff --git a/src/compiler/backend/ia32/instruction-codes-ia32.h b/src/compiler/backend/ia32/instruction-codes-ia32.h index bf163d6845..8d13c950fc 100644 --- a/src/compiler/backend/ia32/instruction-codes-ia32.h +++ b/src/compiler/backend/ia32/instruction-codes-ia32.h @@ -135,6 +135,7 @@ namespace compiler { V(IA32F64x2Le) \ V(IA32I64x2SplatI32Pair) \ V(IA32I64x2ReplaceLaneI32Pair) \ + V(IA32I64x2Neg) \ V(SSEF32x4Splat) \ V(AVXF32x4Splat) \ V(SSEF32x4ExtractLane) \ diff --git a/src/compiler/backend/ia32/instruction-scheduler-ia32.cc b/src/compiler/backend/ia32/instruction-scheduler-ia32.cc index 82094f068b..5a25537577 100644 --- a/src/compiler/backend/ia32/instruction-scheduler-ia32.cc +++ b/src/compiler/backend/ia32/instruction-scheduler-ia32.cc @@ -116,6 +116,7 @@ int InstructionScheduler::GetTargetInstructionFlags( case kIA32F64x2Le: case kIA32I64x2SplatI32Pair: case kIA32I64x2ReplaceLaneI32Pair: + case kIA32I64x2Neg: case kSSEF32x4Splat: case kAVXF32x4Splat: case kSSEF32x4ExtractLane: diff --git a/src/compiler/backend/ia32/instruction-selector-ia32.cc b/src/compiler/backend/ia32/instruction-selector-ia32.cc index 3b18700ec7..19ed0fccac 100644 --- a/src/compiler/backend/ia32/instruction-selector-ia32.cc +++ b/src/compiler/backend/ia32/instruction-selector-ia32.cc @@ -2104,6 +2104,12 @@ void InstructionSelector::VisitI64x2ReplaceLaneI32Pair(Node* node) { low, high); } +void InstructionSelector::VisitI64x2Neg(Node* node) { + IA32OperandGenerator g(this); + InstructionOperand operand0 = g.UseUnique(node->InputAt(0)); + Emit(kIA32I64x2Neg, g.DefineAsRegister(node), operand0); +} + void InstructionSelector::VisitF32x4Splat(Node* node) { VisitRRSimd(this, node, kAVXF32x4Splat, kSSEF32x4Splat); } diff --git a/src/compiler/backend/instruction-selector.cc b/src/compiler/backend/instruction-selector.cc index d8bb174ec3..67c4ffb796 100644 --- a/src/compiler/backend/instruction-selector.cc +++ b/src/compiler/backend/instruction-selector.cc @@ -2659,11 +2659,11 @@ void InstructionSelector::VisitF64x2Lt(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitF64x2Le(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitF64x2Min(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitF64x2Max(Node* node) { UNIMPLEMENTED(); } +void InstructionSelector::VisitI64x2Neg(Node* node) { UNIMPLEMENTED(); } #endif // !V8_TARGET_ARCH_IA32 void InstructionSelector::VisitI64x2Splat(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI64x2ExtractLane(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI64x2ReplaceLane(Node* node) { UNIMPLEMENTED(); } -void InstructionSelector::VisitI64x2Neg(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI64x2Shl(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI64x2ShrS(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI64x2Add(Node* node) { UNIMPLEMENTED(); } diff --git a/test/cctest/wasm/test-run-wasm-simd.cc b/test/cctest/wasm/test-run-wasm-simd.cc index 0ccff874d8..33baac22b6 100644 --- a/test/cctest/wasm/test-run-wasm-simd.cc +++ b/test/cctest/wasm/test-run-wasm-simd.cc @@ -942,7 +942,6 @@ WASM_SIMD_TEST_NO_LOWERING(I64x2ReplaceLane) { } } -#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 void RunI64x2UnOpTest(ExecutionTier execution_tier, LowerSimd lower_simd, WasmOpcode opcode, Int64UnOp expected_op) { WasmRunner r(execution_tier, lower_simd); @@ -969,6 +968,7 @@ WASM_SIMD_TEST_NO_LOWERING(I64x2Neg) { base::NegateWithWraparound); } +#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 void RunI64x2ShiftOpTest(ExecutionTier execution_tier, LowerSimd lower_simd, WasmOpcode opcode, Int64ShiftOp expected_op) { // Intentionally shift by 64, should be no-op.