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[x64] Convert disassembler to use macro list

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SSE2_INSTRUCTION_LIST is unchanged, just sorting by the opcode.
Added ucomisd to the SSE2_UNOP_INSTRUCTION_LIST.
The disassembly for these instructions were mixed with some other
special cases, extracted those out into their own clauses.

Bug: v8:11074
Change-Id: I34871d4bff79d714c006eb5fd96225f7589cf115
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2576886
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Bill Budge <bbudge@chromium.org>
Cr-Commit-Position: refs/heads/master@{#71687}
This commit is contained in:
Zhi An Ng 2020-12-10 03:38:09 +00:00 committed by Commit Bot
parent baf7e9029e
commit 26f9016fca
4 changed files with 57 additions and 228 deletions
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20
src/codegen/x64/assembler-x64.cc
View File

@ -3311,26 +3311,6 @@ void Assembler::haddps(XMMRegister dst, Operand src) {
emit_sse_operand(dst, src);
}
void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0x66);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x2E);
emit_sse_operand(dst, src);
}
void Assembler::ucomisd(XMMRegister dst, Operand src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0x66);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x2E);
emit_sse_operand(dst, src);
}
void Assembler::cmpltsd(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit(0xF2);

8
src/codegen/x64/assembler-x64.h
View File

@ -1229,8 +1229,6 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
void haddps(XMMRegister dst, XMMRegister src);
void haddps(XMMRegister dst, Operand src);
void ucomisd(XMMRegister dst, XMMRegister src);
void ucomisd(XMMRegister dst, Operand src);
void cmpltsd(XMMRegister dst, XMMRegister src);
void movmskpd(Register dst, XMMRegister src);
@ -1461,12 +1459,6 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x2d, idst, xmm0, src, kF2, k0F, kW0);
}
void vucomisd(XMMRegister dst, XMMRegister src) {
vinstr(0x2e, dst, xmm0, src, k66, k0F, kWIG);
}
void vucomisd(XMMRegister dst, Operand src) {
vinstr(0x2e, dst, xmm0, src, k66, k0F, kWIG);
}
void vroundss(XMMRegister dst, XMMRegister src1, XMMRegister src2,
RoundingMode mode) {
vinstr(0x0a, dst, src1, src2, k66, k0F3A, kWIG);

68
src/codegen/x64/sse-instr.h
View File

@ -35,6 +35,7 @@
V(divss, F3, 0F, 5E) \
V(maxss, F3, 0F, 5F)
// Keep sorted by last code.
#define SSE2_INSTRUCTION_LIST(V) \
V(andpd, 66, 0F, 54) \
V(andnpd, 66, 0F, 55) \
@ -44,12 +45,15 @@
V(mulpd, 66, 0F, 59) \
V(subpd, 66, 0F, 5C) \
V(minpd, 66, 0F, 5D) \
V(maxpd, 66, 0F, 5F) \
V(divpd, 66, 0F, 5E) \
V(maxpd, 66, 0F, 5F) \
V(punpcklbw, 66, 0F, 60) \
V(punpcklwd, 66, 0F, 61) \
V(punpckldq, 66, 0F, 62) \
V(packsswb, 66, 0F, 63) \
V(pcmpgtb, 66, 0F, 64) \
V(pcmpgtw, 66, 0F, 65) \
V(pcmpgtd, 66, 0F, 66) \
V(packuswb, 66, 0F, 67) \
V(punpckhbw, 66, 0F, 68) \
V(punpckhwd, 66, 0F, 69) \
@ -57,53 +61,51 @@
V(packssdw, 66, 0F, 6B) \
V(punpcklqdq, 66, 0F, 6C) \
V(punpckhqdq, 66, 0F, 6D) \
V(pmaddwd, 66, 0F, F5) \
V(paddb, 66, 0F, FC) \
V(paddw, 66, 0F, FD) \
V(paddd, 66, 0F, FE) \
V(paddq, 66, 0F, D4) \
V(paddsb, 66, 0F, EC) \
V(paddsw, 66, 0F, ED) \
V(paddusb, 66, 0F, DC) \
V(paddusw, 66, 0F, DD) \
V(pcmpeqb, 66, 0F, 74) \
V(pcmpeqw, 66, 0F, 75) \
V(pcmpeqd, 66, 0F, 76) \
V(pcmpgtb, 66, 0F, 64) \
V(pcmpgtw, 66, 0F, 65) \
V(pcmpgtd, 66, 0F, 66) \
V(pmaxsw, 66, 0F, EE) \
V(pmaxub, 66, 0F, DE) \
V(pminsw, 66, 0F, EA) \
V(pminub, 66, 0F, DA) \
V(psrlw, 66, 0F, D1) \
V(psrld, 66, 0F, D2) \
V(psrlq, 66, 0F, D3) \
V(paddq, 66, 0F, D4) \
V(pmullw, 66, 0F, D5) \
V(pmulhuw, 66, 0F, E4) \
V(pmulhw, 66, 0F, E5) \
V(pmuludq, 66, 0F, F4) \
V(psllw, 66, 0F, F1) \
V(pslld, 66, 0F, F2) \
V(psllq, 66, 0F, F3) \
V(psubusb, 66, 0F, D8) \
V(psubusw, 66, 0F, D9) \
V(pminub, 66, 0F, DA) \
V(pand, 66, 0F, DB) \
V(paddusb, 66, 0F, DC) \
V(paddusw, 66, 0F, DD) \
V(pmaxub, 66, 0F, DE) \
V(pavgb, 66, 0F, E0) \
V(psraw, 66, 0F, E1) \
V(psrad, 66, 0F, E2) \
V(pavgw, 66, 0F, E3) \
V(psrlw, 66, 0F, D1) \
V(psrld, 66, 0F, D2) \
V(psrlq, 66, 0F, D3) \
V(pmulhuw, 66, 0F, E4) \
V(pmulhw, 66, 0F, E5) \
V(psubsb, 66, 0F, E8) \
V(psubsw, 66, 0F, E9) \
V(pminsw, 66, 0F, EA) \
V(por, 66, 0F, EB) \
V(paddsb, 66, 0F, EC) \
V(paddsw, 66, 0F, ED) \
V(pmaxsw, 66, 0F, EE) \
V(pxor, 66, 0F, EF) \
V(psllw, 66, 0F, F1) \
V(pslld, 66, 0F, F2) \
V(psllq, 66, 0F, F3) \
V(pmuludq, 66, 0F, F4) \
V(pmaddwd, 66, 0F, F5) \
V(psubb, 66, 0F, F8) \
V(psubw, 66, 0F, F9) \
V(psubd, 66, 0F, FA) \
V(psubq, 66, 0F, FB) \
V(psubsb, 66, 0F, E8) \
V(psubsw, 66, 0F, E9) \
V(psubusb, 66, 0F, D8) \
V(psubusw, 66, 0F, D9) \
V(pand, 66, 0F, DB) \
V(por, 66, 0F, EB) \
V(pxor, 66, 0F, EF)
V(paddb, 66, 0F, FC) \
V(paddw, 66, 0F, FD) \
V(paddd, 66, 0F, FE)
// SSE2 instructions whose AVX version has two operands.
#define SSE2_UNOP_INSTRUCTION_LIST(V) \
V(ucomisd, 66, 0F, 2E) \
V(sqrtpd, 66, 0F, 51) \
V(cvtps2dq, 66, 0F, 5B)

189
src/diagnostics/x64/disasm-x64.cc
View File

@ -243,6 +243,9 @@ static const InstructionDesc cmov_instructions[16] = {
{"cmovle", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
{"cmovg", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}};
static const char* const cmp_pseudo_op[8] = {"eq", "lt", "le", "unord",
"neq", "nlt", "nle", "ord"};
namespace {
int8_t Imm8(const uint8_t* data) {
return *reinterpret_cast<const int8_t*>(data);
@ -1463,9 +1466,7 @@ int DisassemblerX64::AVXInstruction(byte* data) {
AppendToBuffer("vcmpps %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
const char* const pseudo_op[] = {"eq", "lt", "le", "unord",
"neq", "nlt", "nle", "ord"};
AppendToBuffer(", (%s)", pseudo_op[*current]);
AppendToBuffer(", (%s)", cmp_pseudo_op[*current]);
current += 1;
break;
}
@ -1501,10 +1502,6 @@ int DisassemblerX64::AVXInstruction(byte* data) {
current += PrintRightXMMOperand(current);
AppendToBuffer(",%s", NameOfXMMRegister(regop));
break;
case 0x2E:
AppendToBuffer("vucomisd %s,", NameOfXMMRegister(regop));
current += PrintRightXMMOperand(current);
break;
case 0x50:
AppendToBuffer("vmovmskpd %s,", NameOfCPURegister(regop));
current += PrintRightXMMOperand(current);
@ -1546,9 +1543,7 @@ int DisassemblerX64::AVXInstruction(byte* data) {
AppendToBuffer("vcmppd %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
const char* const pseudo_op[] = {"eq", "lt", "le", "unord",
"neq", "nlt", "nle", "ord"};
AppendToBuffer(", (%s)", pseudo_op[*current]);
AppendToBuffer(", (%s)", cmp_pseudo_op[*current]);
current += 1;
break;
}
@ -1938,167 +1933,29 @@ int DisassemblerX64::TwoByteOpcodeInstruction(byte* data) {
current += 1;
} else if (opcode == 0xB1) {
current += PrintOperands("cmpxchg", OPER_REG_OP_ORDER, current);
} else if (opcode == 0xC2) {
AppendToBuffer("cmppd %s,", NameOfXMMRegister(regop));
current += PrintRightXMMOperand(current);
AppendToBuffer(", (%s)", cmp_pseudo_op[*current++]);
} else if (opcode == 0xC4) {
current += PrintOperands("pinsrw", XMMREG_OPER_OP_ORDER, current);
AppendToBuffer(",0x%x", (*current++) & 7);
} else if (opcode == 0xD7) {
current += PrintOperands("pmovmskb", OPER_XMMREG_OP_ORDER, current);
} else {
const char* mnemonic;
if (opcode == 0x51) {
mnemonic = "sqrtpd";
} else if (opcode == 0x54) {
mnemonic = "andpd";
} else if (opcode == 0x55) {
mnemonic = "andnpd";
} else if (opcode == 0x56) {
mnemonic = "orpd";
} else if (opcode == 0x57) {
mnemonic = "xorpd";
} else if (opcode == 0x58) {
mnemonic = "addpd";
} else if (opcode == 0x59) {
mnemonic = "mulpd";
} else if (opcode == 0x5B) {
mnemonic = "cvtps2dq";
} else if (opcode == 0x5C) {
mnemonic = "subpd";
} else if (opcode == 0x5D) {
mnemonic = "minpd";
} else if (opcode == 0x5E) {
mnemonic = "divpd";
} else if (opcode == 0x5F) {
mnemonic = "maxpd";
} else if (opcode == 0x60) {
mnemonic = "punpcklbw";
} else if (opcode == 0x61) {
mnemonic = "punpcklwd";
} else if (opcode == 0x62) {
mnemonic = "punpckldq";
} else if (opcode == 0x63) {
mnemonic = "packsswb";
} else if (opcode == 0x64) {
mnemonic = "pcmpgtb";
} else if (opcode == 0x65) {
mnemonic = "pcmpgtw";
} else if (opcode == 0x66) {
mnemonic = "pcmpgtd";
} else if (opcode == 0x67) {
mnemonic = "packuswb";
} else if (opcode == 0x68) {
mnemonic = "punpckhbw";
} else if (opcode == 0x69) {
mnemonic = "punpckhwd";
} else if (opcode == 0x6A) {
mnemonic = "punpckhdq";
} else if (opcode == 0x6B) {
mnemonic = "packssdw";
} else if (opcode == 0x6C) {
mnemonic = "punpcklqdq";
} else if (opcode == 0x6D) {
mnemonic = "punpckhqdq";
} else if (opcode == 0x2E) {
mnemonic = "ucomisd";
} else if (opcode == 0x2F) {
mnemonic = "comisd";
} else if (opcode == 0x74) {
mnemonic = "pcmpeqb";
} else if (opcode == 0x75) {
mnemonic = "pcmpeqw";
} else if (opcode == 0x76) {
mnemonic = "pcmpeqd";
} else if (opcode == 0xC2) {
mnemonic = "cmppd";
} else if (opcode == 0xD1) {
mnemonic = "psrlw";
} else if (opcode == 0xD2) {
mnemonic = "psrld";
} else if (opcode == 0xD3) {
mnemonic = "psrlq";
} else if (opcode == 0xD4) {
mnemonic = "paddq";
} else if (opcode == 0xD5) {
mnemonic = "pmullw";
} else if (opcode == 0xD7) {
mnemonic = "pmovmskb";
} else if (opcode == 0xD8) {
mnemonic = "psubusb";
} else if (opcode == 0xD9) {
mnemonic = "psubusw";
} else if (opcode == 0xDA) {
mnemonic = "pminub";
} else if (opcode == 0xDB) {
mnemonic = "pand";
} else if (opcode == 0xDC) {
mnemonic = "paddusb";
} else if (opcode == 0xDD) {
mnemonic = "paddusw";
} else if (opcode == 0xDE) {
mnemonic = "pmaxub";
} else if (opcode == 0xE0) {
mnemonic = "pavgb";
} else if (opcode == 0xE1) {
mnemonic = "psraw";
} else if (opcode == 0xE2) {
mnemonic = "psrad";
} else if (opcode == 0xE3) {
mnemonic = "pavgw";
} else if (opcode == 0xE4) {
mnemonic = "pmulhuw";
} else if (opcode == 0xE5) {
mnemonic = "pmulhw";
} else if (opcode == 0xE8) {
mnemonic = "psubsb";
} else if (opcode == 0xE9) {
mnemonic = "psubsw";
} else if (opcode == 0xEA) {
mnemonic = "pminsw";
} else if (opcode == 0xEB) {
mnemonic = "por";
} else if (opcode == 0xEC) {
mnemonic = "paddsb";
} else if (opcode == 0xED) {
mnemonic = "paddsw";
} else if (opcode == 0xEE) {
mnemonic = "pmaxsw";
} else if (opcode == 0xEF) {
mnemonic = "pxor";
} else if (opcode == 0xF1) {
mnemonic = "psllw";
} else if (opcode == 0xF2) {
mnemonic = "pslld";
} else if (opcode == 0xF3) {
mnemonic = "psllq";
} else if (opcode == 0xF4) {
mnemonic = "pmuludq";
} else if (opcode == 0xF5) {
mnemonic = "pmaddwd";
} else if (opcode == 0xF8) {
mnemonic = "psubb";
} else if (opcode == 0xF9) {
mnemonic = "psubw";
} else if (opcode == 0xFA) {
mnemonic = "psubd";
} else if (opcode == 0xFB) {
mnemonic = "psubq";
} else if (opcode == 0xFC) {
mnemonic = "paddb";
} else if (opcode == 0xFD) {
mnemonic = "paddw";
} else if (opcode == 0xFE) {
mnemonic = "paddd";
} else {
UnimplementedInstruction();
#define SSE2_CASE(instruction, notUsed1, notUsed2, opcode) \
case 0x##opcode: \
mnemonic = "" #instruction; \
break;
switch (opcode) {
SSE2_INSTRUCTION_LIST(SSE2_CASE)
SSE2_UNOP_INSTRUCTION_LIST(SSE2_CASE)
}
// Not every opcode here has an XMM register as the dst operand.
const char* regop_reg =
opcode == 0xD7 ? NameOfCPURegister(regop) : NameOfXMMRegister(regop);
AppendToBuffer("%s %s,", mnemonic, regop_reg);
#undef SSE2_CASE
AppendToBuffer("%s %s,", mnemonic, NameOfXMMRegister(regop));
current += PrintRightXMMOperand(current);
if (opcode == 0xC2) {
const char* const pseudo_op[] = {"eq", "lt", "le", "unord",
"neq", "nlt", "nle", "ord"};
AppendToBuffer(", (%s)", pseudo_op[*current]);
current += 1;
}
}
} else if (group_1_prefix_ == 0xF2) {
// Beginning of instructions with prefix 0xF2.
@ -2284,11 +2141,9 @@ int DisassemblerX64::TwoByteOpcodeInstruction(byte* data) {
current += PrintOperands("xadd", OPER_REG_OP_ORDER, current);
} else if (opcode == 0xC2) {
// cmpps xmm, xmm/m128, imm8
const char* const pseudo_op[] = {"eq", "lt", "le", "unord",
"neq", "nlt", "nle", "ord"};
AppendToBuffer("cmpps %s, ", NameOfXMMRegister(regop));
current += PrintRightXMMOperand(current);
AppendToBuffer(", %s", pseudo_op[*current]);
AppendToBuffer(", %s", cmp_pseudo_op[*current]);
current += 1;
} else if (opcode == 0xC6) {
// shufps xmm, xmm/m128, imm8