AuroraMiddleware/v8
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Turbofan: Rename IsFloat -> IsFP

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Rename some methods to reflect the fact that there are multiple FP
machine representations.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2013193002
Cr-Commit-Position: refs/heads/master@{#36552}
This commit is contained in:
bbudge 2016-05-27 10:43:36 -07:00 committed by Commit bot
parent 5e8f8d4e8c
commit 270a284fd0
6 changed files with 18 additions and 10 deletions
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2
src/compiler/ia32/instruction-selector-ia32.cc
View File

@ -1106,7 +1106,7 @@ void InstructionSelector::EmitPrepareArguments(
g.CanBeImmediate(input.node())
? g.UseImmediate(input.node())
: IsSupported(ATOM) ||
sequence()->IsFloat(GetVirtualRegister(input.node()))
sequence()->IsFP(GetVirtualRegister(input.node()))
? g.UseRegister(input.node())
: g.Use(input.node());
if (input.type() == MachineType::Float32()) {

10
src/compiler/instruction.h
View File

@ -1323,9 +1323,17 @@ class InstructionSequence final : public ZoneObject {
return GetRepresentation(virtual_register) ==
MachineRepresentation::kTagged;
}
bool IsFloat(int virtual_register) const {
bool IsFP(int virtual_register) const {
return IsFloatingPoint(GetRepresentation(virtual_register));
}
bool IsFloat(int virtual_register) const {
return GetRepresentation(virtual_register) ==
MachineRepresentation::kFloat32;
}
bool IsDouble(int virtual_register) const {
return GetRepresentation(virtual_register) ==
MachineRepresentation::kFloat64;
}
Instruction* GetBlockStart(RpoNumber rpo) const;

8
src/compiler/register-allocator-verifier.cc
View File

@ -160,13 +160,13 @@ void RegisterAllocatorVerifier::BuildConstraint(const InstructionOperand* op,
int vreg = unallocated->virtual_register();
constraint->virtual_register_ = vreg;
if (unallocated->basic_policy() == UnallocatedOperand::FIXED_SLOT) {
constraint->type_ = sequence()->IsFloat(vreg) ? kDoubleSlot : kSlot;
constraint->type_ = sequence()->IsFP(vreg) ? kDoubleSlot : kSlot;
constraint->value_ = unallocated->fixed_slot_index();
} else {
switch (unallocated->extended_policy()) {
case UnallocatedOperand::ANY:
case UnallocatedOperand::NONE:
if (sequence()->IsFloat(vreg)) {
if (sequence()->IsFP(vreg)) {
constraint->type_ = kNoneDouble;
} else {
constraint->type_ = kNone;
@ -186,14 +186,14 @@ void RegisterAllocatorVerifier::BuildConstraint(const InstructionOperand* op,
constraint->value_ = unallocated->fixed_register_index();
break;
case UnallocatedOperand::MUST_HAVE_REGISTER:
if (sequence()->IsFloat(vreg)) {
if (sequence()->IsFP(vreg)) {
constraint->type_ = kDoubleRegister;
} else {
constraint->type_ = kRegister;
}
break;
case UnallocatedOperand::MUST_HAVE_SLOT:
constraint->type_ = sequence()->IsFloat(vreg) ? kDoubleSlot : kSlot;
constraint->type_ = sequence()->IsFP(vreg) ? kDoubleSlot : kSlot;
break;
case UnallocatedOperand::SAME_AS_FIRST_INPUT:
constraint->type_ = kSameAsFirst;

2
src/compiler/x64/instruction-selector-x64.cc
View File

@ -1440,7 +1440,7 @@ void InstructionSelector::EmitPrepareArguments(
g.CanBeImmediate(input.node())
? g.UseImmediate(input.node())
: IsSupported(ATOM) ||
sequence()->IsFloat(GetVirtualRegister(input.node()))
sequence()->IsFP(GetVirtualRegister(input.node()))
? g.UseRegister(input.node())
: g.Use(input.node());
Emit(kX64Push, g.NoOutput(), value);

2
src/compiler/x87/instruction-selector-x87.cc
View File

@ -1121,7 +1121,7 @@ void InstructionSelector::EmitPrepareArguments(
g.CanBeImmediate(input.node())
? g.UseImmediate(input.node())
: IsSupported(ATOM) ||
sequence()->IsFloat(GetVirtualRegister(input.node()))
sequence()->IsFP(GetVirtualRegister(input.node()))
? g.UseRegister(input.node())
: g.Use(input.node());
Emit(kX87Push, g.NoOutput(), value);

4
test/unittests/compiler/instruction-selector-unittest.cc
View File

@ -94,12 +94,12 @@ InstructionSelectorTest::Stream InstructionSelectorTest::StreamBuilder::Build(
}
for (auto i : s.virtual_registers_) {
int const virtual_register = i.second;
if (sequence.IsFloat(virtual_register)) {
if (sequence.IsFP(virtual_register)) {
EXPECT_FALSE(sequence.IsReference(virtual_register));
s.doubles_.insert(virtual_register);
}
if (sequence.IsReference(virtual_register)) {
EXPECT_FALSE(sequence.IsFloat(virtual_register));
EXPECT_FALSE(sequence.IsFP(virtual_register));
s.references_.insert(virtual_register);
}
}