From 2ac469ae5d4545b7c01353f44120e3ee52c284b9 Mon Sep 17 00:00:00 2001 From: Liu Yu Date: Wed, 6 Jul 2022 16:38:48 +0800 Subject: [PATCH] [loong64][mips64][fastcall] Support EnforceRange annotation Port commit 8559a04f4ce6cbaa95831ffde18f9e89be0d53fe Change-Id: I74bbbaddb196bba0945cc857e708534e4eb3f9b3 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3747466 Reviewed-by: Maya Lekova Commit-Queue: Maya Lekova Auto-Submit: Liu Yu Cr-Commit-Position: refs/heads/main@{#81551} --- src/compiler/backend/code-generator-impl.h | 4 +++ .../backend/loong64/code-generator-loong64.cc | 19 +++++++++++ .../loong64/instruction-selector-loong64.cc | 32 +++++++++++++++++++ .../backend/mips64/code-generator-mips64.cc | 19 +++++++++++ .../mips64/instruction-selector-mips64.cc | 32 +++++++++++++++++++ test/mjsunit/mjsunit.status | 2 +- 6 files changed, 107 insertions(+), 1 deletion(-) diff --git a/src/compiler/backend/code-generator-impl.h b/src/compiler/backend/code-generator-impl.h index 87066c5bd3..df463396e5 100644 --- a/src/compiler/backend/code-generator-impl.h +++ b/src/compiler/backend/code-generator-impl.h @@ -116,6 +116,10 @@ class InstructionOperandConverter { return ToDoubleRegister(instr_->Output()); } + DoubleRegister TempDoubleRegister(size_t index) { + return ToDoubleRegister(instr_->TempAt(index)); + } + Simd128Register OutputSimd128Register() { return ToSimd128Register(instr_->Output()); } diff --git a/src/compiler/backend/loong64/code-generator-loong64.cc b/src/compiler/backend/loong64/code-generator-loong64.cc index 23b03be674..eb446c7b9c 100644 --- a/src/compiler/backend/loong64/code-generator-loong64.cc +++ b/src/compiler/backend/loong64/code-generator-loong64.cc @@ -1340,6 +1340,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( FPURegister scratch = kScratchDoubleReg; __ ftintrz_w_d(scratch, i.InputDoubleRegister(0)); __ movfr2gr_s(i.OutputRegister(), scratch); + if (instr->OutputCount() > 1) { + // Check for inputs below INT32_MIN and NaN. + __ li(i.OutputRegister(1), 1); + __ Move(i.TempDoubleRegister(0), static_cast(INT32_MIN)); + __ CompareF64(i.TempDoubleRegister(0), i.InputDoubleRegister(0), CLE); + __ LoadZeroIfNotFPUCondition(i.OutputRegister(1)); + __ Move(i.TempDoubleRegister(0), static_cast(INT32_MAX) + 1); + __ CompareF64(i.TempDoubleRegister(0), i.InputDoubleRegister(0), CLE); + __ LoadZeroIfFPUCondition(i.OutputRegister(1)); + } break; } case kLoong64Float32ToInt32: { @@ -1407,6 +1417,15 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( case kLoong64Float64ToUint32: { FPURegister scratch = kScratchDoubleReg; __ Ftintrz_uw_d(i.OutputRegister(), i.InputDoubleRegister(0), scratch); + if (instr->OutputCount() > 1) { + __ li(i.OutputRegister(1), 1); + __ Move(i.TempDoubleRegister(0), static_cast(-1.0)); + __ CompareF64(i.TempDoubleRegister(0), i.InputDoubleRegister(0), CLT); + __ LoadZeroIfNotFPUCondition(i.OutputRegister(1)); + __ Move(i.TempDoubleRegister(0), static_cast(UINT32_MAX) + 1); + __ CompareF64(i.TempDoubleRegister(0), i.InputDoubleRegister(0), CLE); + __ LoadZeroIfFPUCondition(i.OutputRegister(1)); + } break; } case kLoong64Float32ToUint32: { diff --git a/src/compiler/backend/loong64/instruction-selector-loong64.cc b/src/compiler/backend/loong64/instruction-selector-loong64.cc index eb45a45ed1..467d9b4e1c 100644 --- a/src/compiler/backend/loong64/instruction-selector-loong64.cc +++ b/src/compiler/backend/loong64/instruction-selector-loong64.cc @@ -1353,6 +1353,38 @@ void InstructionSelector::VisitTryTruncateFloat64ToUint64(Node* node) { Emit(kLoong64Float64ToUint64, output_count, outputs, 1, inputs); } +void InstructionSelector::VisitTryTruncateFloat64ToInt32(Node* node) { + Loong64OperandGenerator g(this); + InstructionOperand inputs[] = {g.UseRegister(node->InputAt(0))}; + InstructionOperand temps[] = {g.TempDoubleRegister()}; + InstructionOperand outputs[2]; + size_t output_count = 0; + outputs[output_count++] = g.DefineAsRegister(node); + + Node* success_output = NodeProperties::FindProjection(node, 1); + if (success_output) { + outputs[output_count++] = g.DefineAsRegister(success_output); + } + + Emit(kLoong64Float64ToInt32, output_count, outputs, 1, inputs, 1, temps); +} + +void InstructionSelector::VisitTryTruncateFloat64ToUint32(Node* node) { + Loong64OperandGenerator g(this); + InstructionOperand inputs[] = {g.UseRegister(node->InputAt(0))}; + InstructionOperand temps[] = {g.TempDoubleRegister()}; + InstructionOperand outputs[2]; + size_t output_count = 0; + outputs[output_count++] = g.DefineAsRegister(node); + + Node* success_output = NodeProperties::FindProjection(node, 1); + if (success_output) { + outputs[output_count++] = g.DefineAsRegister(success_output); + } + + Emit(kLoong64Float64ToUint32, output_count, outputs, 1, inputs, 1, temps); +} + void InstructionSelector::VisitBitcastWord32ToWord64(Node* node) { UNIMPLEMENTED(); } diff --git a/src/compiler/backend/mips64/code-generator-mips64.cc b/src/compiler/backend/mips64/code-generator-mips64.cc index 24552bbe79..2f777cf121 100644 --- a/src/compiler/backend/mips64/code-generator-mips64.cc +++ b/src/compiler/backend/mips64/code-generator-mips64.cc @@ -1462,6 +1462,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( // Other arches use round to zero here, so we follow. __ trunc_w_d(scratch, i.InputDoubleRegister(0)); __ mfc1(i.OutputRegister(), scratch); + if (instr->OutputCount() > 1) { + // Check for inputs below INT32_MIN and NaN. + __ li(i.OutputRegister(1), 1); + __ Move(i.TempDoubleRegister(0), static_cast(INT32_MIN)); + __ CompareF64(LE, i.TempDoubleRegister(0), i.InputDoubleRegister(0)); + __ LoadZeroIfNotFPUCondition(i.OutputRegister(1)); + __ Move(i.TempDoubleRegister(0), static_cast(INT32_MAX) + 1); + __ CompareF64(LE, i.TempDoubleRegister(0), i.InputDoubleRegister(0)); + __ LoadZeroIfFPUCondition(i.OutputRegister(1)); + } break; } case kMips64FloorWS: { @@ -1546,6 +1556,15 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( case kMips64TruncUwD: { FPURegister scratch = kScratchDoubleReg; __ Trunc_uw_d(i.OutputRegister(), i.InputDoubleRegister(0), scratch); + if (instr->OutputCount() > 1) { + __ li(i.OutputRegister(1), 1); + __ Move(i.TempDoubleRegister(0), static_cast(-1.0)); + __ CompareF64(LT, i.TempDoubleRegister(0), i.InputDoubleRegister(0)); + __ LoadZeroIfNotFPUCondition(i.OutputRegister(1)); + __ Move(i.TempDoubleRegister(0), static_cast(UINT32_MAX) + 1); + __ CompareF64(LE, i.TempDoubleRegister(0), i.InputDoubleRegister(0)); + __ LoadZeroIfFPUCondition(i.OutputRegister(1)); + } break; } case kMips64TruncUwS: { diff --git a/src/compiler/backend/mips64/instruction-selector-mips64.cc b/src/compiler/backend/mips64/instruction-selector-mips64.cc index d1df16e622..787ce44183 100644 --- a/src/compiler/backend/mips64/instruction-selector-mips64.cc +++ b/src/compiler/backend/mips64/instruction-selector-mips64.cc @@ -1436,6 +1436,38 @@ void InstructionSelector::VisitTryTruncateFloat64ToUint64(Node* node) { Emit(kMips64TruncUlD, output_count, outputs, 1, inputs); } +void InstructionSelector::VisitTryTruncateFloat64ToInt32(Node* node) { + Mips64OperandGenerator g(this); + InstructionOperand inputs[] = {g.UseRegister(node->InputAt(0))}; + InstructionOperand temps[] = {g.TempDoubleRegister()}; + InstructionOperand outputs[2]; + size_t output_count = 0; + outputs[output_count++] = g.DefineAsRegister(node); + + Node* success_output = NodeProperties::FindProjection(node, 1); + if (success_output) { + outputs[output_count++] = g.DefineAsRegister(success_output); + } + + Emit(kMips64TruncWD, output_count, outputs, 1, inputs, 1, temps); +} + +void InstructionSelector::VisitTryTruncateFloat64ToUint32(Node* node) { + Mips64OperandGenerator g(this); + InstructionOperand inputs[] = {g.UseRegister(node->InputAt(0))}; + InstructionOperand temps[] = {g.TempDoubleRegister()}; + InstructionOperand outputs[2]; + size_t output_count = 0; + outputs[output_count++] = g.DefineAsRegister(node); + + Node* success_output = NodeProperties::FindProjection(node, 1); + if (success_output) { + outputs[output_count++] = g.DefineAsRegister(success_output); + } + + Emit(kMips64TruncUwD, output_count, outputs, 1, inputs, 1, temps); +} + void InstructionSelector::VisitBitcastWord32ToWord64(Node* node) { UNIMPLEMENTED(); } diff --git a/test/mjsunit/mjsunit.status b/test/mjsunit/mjsunit.status index 293bda9a50..67b02b654e 100644 --- a/test/mjsunit/mjsunit.status +++ b/test/mjsunit/mjsunit.status @@ -1713,7 +1713,7 @@ }], # arch != x64 ############################################################################## -['arch != x64 and arch != arm64', { +['arch != x64 and arch != arm64 and arch != loong64 and arch != mips64', { # Tests that include types only supported on x64/arm64. 'compiler/fast-api-sequences-x64': [SKIP], 'compiler/fast-api-annotations': [SKIP],