AuroraMiddleware/v8
1
0
Fork 0
Code Issues 2 Pull Requests Releases Wiki Activity

[arm64] Turn off the default NaN mode on arm64.

Browse Source 
The default NaN mode was originally used to identify holes in double
arrays. With (https://codereview.chromium.org/863633002/) signalling
NaNs are used for that, and the default NaN mode is not needed anymore.
Without the default NaN mode it is easier to satisfy the WebAssembly
spec which requires that quiet NaNs are preserved.

R=titzer@chromium.org, rodolph.perfetta@arm.com, bmeurer@chromium.org

Review URL: https://codereview.chromium.org/1884193002

Cr-Commit-Position: refs/heads/master@{#35518}
This commit is contained in:
ahaas 2016-04-15 04:50:41 -07:00 committed by Commit bot
parent 62cca39e6c
commit 2f9eb09f20
4 changed files with 4 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/arm64/code-stubs-arm64.cc
View File

@ -1323,11 +1323,6 @@ void JSEntryStub::Generate(MacroAssembler* masm) {
__ Mov(jssp, csp);
__ SetStackPointer(jssp);
// Configure the FPCR. We don't restore it, so this is technically not allowed
// according to AAPCS64. However, we only set default-NaN mode and this will
// be harmless for most C code. Also, it works for ARM.
__ ConfigureFPCR();
ProfileEntryHookStub::MaybeCallEntryHook(masm);
// Set up the reserved register for 0.0.

28
src/arm64/macro-assembler-arm64.cc
View File

@ -1373,10 +1373,6 @@ void MacroAssembler::AssertFPCRState(Register fpcr) {
Mrs(fpcr, FPCR);
}
// Settings overridden by ConfiugreFPCR():
// - Assert that default-NaN mode is set.
Tbz(fpcr, DN_offset, &unexpected_mode);
// Settings left to their default values:
// - Assert that flush-to-zero is not set.
Tbnz(fpcr, FZ_offset, &unexpected_mode);
@ -1393,31 +1389,13 @@ void MacroAssembler::AssertFPCRState(Register fpcr) {
}
void MacroAssembler::ConfigureFPCR() {
UseScratchRegisterScope temps(this);
Register fpcr = temps.AcquireX();
Mrs(fpcr, FPCR);
// If necessary, enable default-NaN mode. The default values of the other FPCR
// options should be suitable, and AssertFPCRState will verify that.
Label no_write_required;
Tbnz(fpcr, DN_offset, &no_write_required);
Orr(fpcr, fpcr, DN_mask);
Msr(FPCR, fpcr);
Bind(&no_write_required);
AssertFPCRState(fpcr);
}
void MacroAssembler::CanonicalizeNaN(const FPRegister& dst,
const FPRegister& src) {
AssertFPCRState();
// With DN=1 and RMode=FPTieEven, subtracting 0.0 preserves all inputs except
// for NaNs, which become the default NaN. We use fsub rather than fadd
// because sub preserves -0.0 inputs: -0.0 + 0.0 = 0.0, but -0.0 - 0.0 = -0.0.
// Subtracting 0.0 preserves all inputs except for signalling NaNs, which
// become quiet NaNs. We use fsub rather than fadd because fsub preserves -0.0
// inputs: -0.0 + 0.0 = 0.0, but -0.0 - 0.0 = -0.0.
Fsub(dst, src, fp_zero);
}

1
src/arm64/macro-assembler-arm64.h
View File

@ -865,7 +865,6 @@ class MacroAssembler : public Assembler {
inline void InitializeRootRegister();
void AssertFPCRState(Register fpcr = NoReg);
void ConfigureFPCR();
void CanonicalizeNaN(const FPRegister& dst, const FPRegister& src);
void CanonicalizeNaN(const FPRegister& reg) {
CanonicalizeNaN(reg, reg);

3
test/cctest/wasm/test-run-wasm.cc
View File

@ -2631,8 +2631,7 @@ TEST(Run_Wasm_F64Max) {
}
// TODO(ahaas): Fix on arm and mips and reenable.
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS && \
!V8_TARGET_ARCH_MIPS64
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
TEST(Run_Wasm_F32Min_Snan) {
// Test that the instruction does not return a signalling NaN.